* [PATCH_v3 0/2] Add Q6SSTOP clock controller for QCS404 @ 2019-08-23 13:13 Govind Singh 2019-08-23 13:14 ` [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings Govind Singh 2019-08-23 13:14 ` [PATCH_v3 2/2] clk: qcom: Add Q6SSTOP clock controller for QCS404 Govind Singh 0 siblings, 2 replies; 6+ messages in thread From: Govind Singh @ 2019-08-23 13:13 UTC (permalink / raw) To: sboyd, robh Cc: bjorn.andersson, linux-arm-msm, linux-clk, devicetree, linux-soc, linux-remoteproc, Govind Singh Add support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP. Changes in v3: - Fixed dt binding errors. Changes in v2: - changed binding doc to yaml format. - Fixed alignment in q6sstop cc driver. Govind Singh (2): dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings clk: qcom: Add Q6SSTOP clock controller for QCS404 .../bindings/clock/qcom,q6sstopcc.yaml | 47 ++++ drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/q6sstop-qcs404.c | 223 ++++++++++++++++++ .../dt-bindings/clock/qcom,q6sstopcc-qcs404.h | 18 ++ 5 files changed, 297 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml create mode 100644 drivers/clk/qcom/q6sstop-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings 2019-08-23 13:13 [PATCH_v3 0/2] Add Q6SSTOP clock controller for QCS404 Govind Singh @ 2019-08-23 13:14 ` Govind Singh 2019-08-27 12:27 ` Rob Herring 2019-08-23 13:14 ` [PATCH_v3 2/2] clk: qcom: Add Q6SSTOP clock controller for QCS404 Govind Singh 1 sibling, 1 reply; 6+ messages in thread From: Govind Singh @ 2019-08-23 13:14 UTC (permalink / raw) To: sboyd, robh Cc: bjorn.andersson, linux-arm-msm, linux-clk, devicetree, linux-soc, linux-remoteproc, Govind Singh Add devicetree binding for the Q6SSTOP clock controller found in QCS404. Signed-off-by: Govind Singh <govinds@codeaurora.org> --- .../bindings/clock/qcom,q6sstopcc.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml new file mode 100644 index 000000000000..39621e2e2f4e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,q6sstopcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Q6SSTOP clock Controller + +maintainers: + - Govind Singh <govinds@codeaurora.org> + +description: + Q6SSTOP clock controller is used by WCSS remoteproc driver + to bring WDSP out of reset. + +properties: + compatible: + const: "qcom,qcs404-q6sstopcc" + + reg: + items: + - description: Q6SSTOP clocks register region + - description: Q6SSTOP_TCSR register region + + clocks: + items: + - description: ahb clock for the q6sstopCC + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + q6sstopcc: clock-controller@7500000 { + compatible = "qcom,qcs404-q6sstopcc"; + reg = <0x07500000 0x4e000>, <0x07550000 0x10000>; + clocks = <&gcc 141>; + #clock-cells = <1>; + }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings 2019-08-23 13:14 ` [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings Govind Singh @ 2019-08-27 12:27 ` Rob Herring 2019-09-06 20:31 ` Stephen Boyd 0 siblings, 1 reply; 6+ messages in thread From: Rob Herring @ 2019-08-27 12:27 UTC (permalink / raw) To: Govind Singh Cc: Stephen Boyd, Bjorn Andersson, linux-arm-msm, linux-clk, devicetree, open list:ARM/QUALCOMM SUPPORT, open list:REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM On Fri, Aug 23, 2019 at 8:14 AM Govind Singh <govinds@codeaurora.org> wrote: > > Add devicetree binding for the Q6SSTOP clock controller found in QCS404. > > Signed-off-by: Govind Singh <govinds@codeaurora.org> > --- > .../bindings/clock/qcom,q6sstopcc.yaml | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > > diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > new file mode 100644 > index 000000000000..39621e2e2f4e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > @@ -0,0 +1,47 @@ > +# SPDX-License-Identifier: BSD-2-Clause Dual license please. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,q6sstopcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Q6SSTOP clock Controller > + > +maintainers: > + - Govind Singh <govinds@codeaurora.org> > + > +description: > + Q6SSTOP clock controller is used by WCSS remoteproc driver What driver for some OS is not relevant to the binding. > + to bring WDSP out of reset. > + > +properties: > + compatible: > + const: "qcom,qcs404-q6sstopcc" > + > + reg: > + items: > + - description: Q6SSTOP clocks register region > + - description: Q6SSTOP_TCSR register region > + > + clocks: > + items: > + - description: ahb clock for the q6sstopCC > + > + '#clock-cells': > + const: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + q6sstopcc: clock-controller@7500000 { > + compatible = "qcom,qcs404-q6sstopcc"; > + reg = <0x07500000 0x4e000>, <0x07550000 0x10000>; > + clocks = <&gcc 141>; > + #clock-cells = <1>; > + }; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings 2019-08-27 12:27 ` Rob Herring @ 2019-09-06 20:31 ` Stephen Boyd 2019-10-11 13:35 ` Govind Singh 0 siblings, 1 reply; 6+ messages in thread From: Stephen Boyd @ 2019-09-06 20:31 UTC (permalink / raw) To: Govind Singh, Rob Herring Cc: Bjorn Andersson, linux-arm-msm, linux-clk, devicetree, open list:ARM/QUALCOMM SUPPORT, open list:REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM Quoting Rob Herring (2019-08-27 05:27:19) > On Fri, Aug 23, 2019 at 8:14 AM Govind Singh <govinds@codeaurora.org> wrote: > > > > Add devicetree binding for the Q6SSTOP clock controller found in QCS404. > > > > Signed-off-by: Govind Singh <govinds@codeaurora.org> > > --- > > .../bindings/clock/qcom,q6sstopcc.yaml | 47 +++++++++++++++++++ > > 1 file changed, 47 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > > new file mode 100644 > > index 000000000000..39621e2e2f4e > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml > > @@ -0,0 +1,47 @@ > > +# SPDX-License-Identifier: BSD-2-Clause > > Dual license please. > Yes, please fix the binding. ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings 2019-09-06 20:31 ` Stephen Boyd @ 2019-10-11 13:35 ` Govind Singh 0 siblings, 0 replies; 6+ messages in thread From: Govind Singh @ 2019-10-11 13:35 UTC (permalink / raw) To: Stephen Boyd Cc: Rob Herring, Bjorn Andersson, linux-arm-msm, linux-clk, devicetree, open list:ARM/QUALCOMM SUPPORT, open list:REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM On 2019-09-07 02:01, Stephen Boyd wrote: > Quoting Rob Herring (2019-08-27 05:27:19) >> On Fri, Aug 23, 2019 at 8:14 AM Govind Singh <govinds@codeaurora.org> >> wrote: >> > >> > Add devicetree binding for the Q6SSTOP clock controller found in QCS404. >> > >> > Signed-off-by: Govind Singh <govinds@codeaurora.org> >> > --- >> > .../bindings/clock/qcom,q6sstopcc.yaml | 47 +++++++++++++++++++ >> > 1 file changed, 47 insertions(+) >> > create mode 100644 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml >> > >> > diff --git a/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml >> > new file mode 100644 >> > index 000000000000..39621e2e2f4e >> > --- /dev/null >> > +++ b/Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml >> > @@ -0,0 +1,47 @@ >> > +# SPDX-License-Identifier: BSD-2-Clause >> >> Dual license please. >> > > Yes, please fix the binding. fixed in v4. Thanks, Govind ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH_v3 2/2] clk: qcom: Add Q6SSTOP clock controller for QCS404 2019-08-23 13:13 [PATCH_v3 0/2] Add Q6SSTOP clock controller for QCS404 Govind Singh 2019-08-23 13:14 ` [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings Govind Singh @ 2019-08-23 13:14 ` Govind Singh 1 sibling, 0 replies; 6+ messages in thread From: Govind Singh @ 2019-08-23 13:14 UTC (permalink / raw) To: sboyd, robh Cc: bjorn.andersson, linux-arm-msm, linux-clk, devicetree, linux-soc, linux-remoteproc, Govind Singh Add support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP. Signed-off-by: Govind Singh <govinds@codeaurora.org> --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/q6sstop-qcs404.c | 223 ++++++++++++++++++ .../dt-bindings/clock/qcom,q6sstopcc-qcs404.h | 18 ++ 4 files changed, 250 insertions(+) create mode 100644 drivers/clk/qcom/q6sstop-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e1ff83cc361e..1b3c87a97521 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -250,6 +250,14 @@ config QCS_TURING_404 Support for the Turing Clock Controller on QCS404, provides clocks and resets for the Turing subsystem. +config QCS_Q6SSTOP_404 + tristate "QCS404 Q6SSTOP Clock Controller" + select QCS_GCC_404 + help + Support for the Q6SSTOP clock controller on QCS404 devices. + Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock + controller to reset the Q6SSTOP subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f0768fb1f037..086c053e0e03 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o +obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o diff --git a/drivers/clk/qcom/q6sstop-qcs404.c b/drivers/clk/qcom/q6sstop-qcs404.c new file mode 100644 index 000000000000..b0f54a4c9365 --- /dev/null +++ b/drivers/clk/qcom/q6sstop-qcs404.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,q6sstopcc-qcs404.h> + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" +#include "reset.h" + +static struct clk_branch lcc_ahbfabric_cbc_clk = { + .halt_reg = 0x1b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_ahbfabric_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_ahbs_cbc_clk = { + .halt_reg = 0x22000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x22000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_ahbs_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = { + .halt_reg = 0x1c000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_tcm_slave_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_ahbm_cbc_clk = { + .halt_reg = 0x22004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x22004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_ahbm_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_axim_cbc_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_axim_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_bcr_sleep_clk = { + .halt_reg = 0x6004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x6004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_bcr_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* TCSR clock */ +static struct clk_branch tcsr_lcc_csr_cbcr_clk = { + .halt_reg = 0x8008, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x8008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_lcc_csr_cbcr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config q6sstop_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *q6sstop_qcs404_clocks[] = { + [LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr, + [LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr, + [LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr, + [LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr, + [LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr, + [LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr, +}; + +static const struct qcom_reset_map q6sstop_qcs404_resets[] = { + [Q6SSTOP_BCR_RESET] = { 0x6000 }, +}; + +static const struct qcom_cc_desc q6sstop_qcs404_desc = { + .config = &q6sstop_regmap_config, + .clks = q6sstop_qcs404_clocks, + .num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks), + .resets = q6sstop_qcs404_resets, + .num_resets = ARRAY_SIZE(q6sstop_qcs404_resets), +}; + +static struct clk_regmap *tcsr_qcs404_clocks[] = { + [TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr, +}; + +static const struct qcom_cc_desc tcsr_qcs404_desc = { + .config = &q6sstop_regmap_config, + .clks = tcsr_qcs404_clocks, + .num_clks = ARRAY_SIZE(tcsr_qcs404_clocks), +}; + +static const struct of_device_id q6sstopcc_qcs404_match_table[] = { + { .compatible = "qcom,qcs404-q6sstopcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table); + +static int q6sstopcc_qcs404_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + q6sstop_regmap_config.name = "q6sstop_tcsr"; + desc = &tcsr_qcs404_desc; + + ret = qcom_cc_probe_by_index(pdev, 1, desc); + if (ret) + goto destroy_pm_clk; + + q6sstop_regmap_config.name = "q6sstop_cc"; + desc = &q6sstop_qcs404_desc; + + ret = qcom_cc_probe_by_index(pdev, 0, desc); + if (ret) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int q6sstopcc_qcs404_remove(struct platform_device *pdev) +{ + pm_clk_destroy(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct dev_pm_ops q6sstopcc_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver q6sstopcc_qcs404_driver = { + .probe = q6sstopcc_qcs404_probe, + .remove = q6sstopcc_qcs404_remove, + .driver = { + .name = "qcs404-q6sstopcc", + .of_match_table = q6sstopcc_qcs404_match_table, + .pm = &q6sstopcc_pm_ops, + }, +}; + +module_platform_driver(q6sstopcc_qcs404_driver); + +MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h new file mode 100644 index 000000000000..c6f5290f0914 --- /dev/null +++ b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H + +#define LCC_AHBFABRIC_CBC_CLK 0 +#define LCC_Q6SS_AHBS_CBC_CLK 1 +#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 +#define LCC_Q6SS_AHBM_CBC_CLK 3 +#define LCC_Q6SS_AXIM_CBC_CLK 4 +#define LCC_Q6SS_BCR_SLEEP_CLK 5 +#define TCSR_Q6SS_LCC_CBCR_CLK 6 + +#define Q6SSTOP_BCR_RESET 1 +#endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-11 13:35 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-08-23 13:13 [PATCH_v3 0/2] Add Q6SSTOP clock controller for QCS404 Govind Singh 2019-08-23 13:14 ` [PATCH_v3 1/2] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings Govind Singh 2019-08-27 12:27 ` Rob Herring 2019-09-06 20:31 ` Stephen Boyd 2019-10-11 13:35 ` Govind Singh 2019-08-23 13:14 ` [PATCH_v3 2/2] clk: qcom: Add Q6SSTOP clock controller for QCS404 Govind Singh
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