* [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
@ 2019-12-18 18:44 Dmitry Osipenko
2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dmitry Osipenko @ 2019-12-18 18:44 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Prashant Gaikwad, Michael Turquette, Stephen Boyd
Cc: linux-tegra, linux-clk, linux-kernel
UART clock is divided using divisor values from DLM/DLL registers when
enable-bit is unset in clk register and clk's divider configuration isn't
taken onto account in this case. This doesn't cause any problems, but
let's add a check for the divider's enable-bit state, for consistency.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-divider.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index ca0de5f11f84..38daf483ddf1 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
int div, mul;
u64 rate = parent_rate;
- reg = readl_relaxed(divider->reg) >> divider->shift;
- div = reg & div_mask(divider);
+ reg = readl_relaxed(divider->reg);
+
+ if ((divider->flags & TEGRA_DIVIDER_UART) &&
+ !(reg & PERIPH_CLK_UART_DIV_ENB))
+ return rate;
+
+ div = (reg >> divider->shift) & div_mask(divider);
mul = get_mul(divider);
div += mul;
--
2.24.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock 2019-12-18 18:44 [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko @ 2019-12-18 18:44 ` Dmitry Osipenko 2020-01-07 23:21 ` Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 3/3] clk: tegra20/30: Explicitly set parent clock for Video Decoder Dmitry Osipenko 2020-01-10 14:52 ` [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Thierry Reding 2 siblings, 1 reply; 5+ messages in thread From: Dmitry Osipenko @ 2019-12-18 18:44 UTC (permalink / raw) To: Thierry Reding, Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Michael Turquette, Stephen Boyd Cc: linux-tegra, linux-clk, linux-kernel Both Tegra20 and Tegra30 are initializing display's parent clock incorrectly because PLLP is running at 216/408MHz while display rate is set to 600MHz, but pre-setting the parent isn't needed at all because display driver selects proper parent anyways. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 2 -- drivers/clk/tegra/clk-tegra30.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 4d8222f5c638..0c14fb570343 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1046,8 +1046,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, - { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 }, - { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c8bc18e4d7e5..bd4d42005897 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1251,8 +1251,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, - { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, - { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, -- 2.24.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko @ 2020-01-07 23:21 ` Dmitry Osipenko 0 siblings, 0 replies; 5+ messages in thread From: Dmitry Osipenko @ 2020-01-07 23:21 UTC (permalink / raw) To: Thierry Reding, Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Michael Turquette, Stephen Boyd Cc: linux-tegra, linux-clk, linux-kernel 18.12.2019 21:44, Dmitry Osipenko пишет: > Both Tegra20 and Tegra30 are initializing display's parent clock > incorrectly because PLLP is running at 216/408MHz while display rate is > set to 600MHz, but pre-setting the parent isn't needed at all because > display driver selects proper parent anyways. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/clk/tegra/clk-tegra20.c | 2 -- > drivers/clk/tegra/clk-tegra30.c | 2 -- > 2 files changed, 4 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index 4d8222f5c638..0c14fb570343 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -1046,8 +1046,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { > { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, > { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 }, > { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, > - { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 }, > - { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 }, > { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, > diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c > index c8bc18e4d7e5..bd4d42005897 100644 > --- a/drivers/clk/tegra/clk-tegra30.c > +++ b/drivers/clk/tegra/clk-tegra30.c > @@ -1251,8 +1251,6 @@ static struct tegra_clk_init_table init_table[] __initdata = { > { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 }, > { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, > { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 }, > - { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 }, > - { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 }, > { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 }, > { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 }, > { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, > Hello people, Could anyone please take a look at these trivial patches and give an ACK? Thanks in advance! ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH RESEND for 5.6 v1 3/3] clk: tegra20/30: Explicitly set parent clock for Video Decoder 2019-12-18 18:44 [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko @ 2019-12-18 18:44 ` Dmitry Osipenko 2020-01-10 14:52 ` [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Thierry Reding 2 siblings, 0 replies; 5+ messages in thread From: Dmitry Osipenko @ 2019-12-18 18:44 UTC (permalink / raw) To: Thierry Reding, Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Michael Turquette, Stephen Boyd Cc: linux-tegra, linux-clk, linux-kernel The VDE parent won't be changed automatically to PLLC if bootloader didn't do that for us, hence let's explicitly set the parent for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 0c14fb570343..fff5cba87637 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1048,7 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 }, { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, - { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 }, + { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index bd4d42005897..b20891489e11 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1256,7 +1256,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, -- 2.24.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation 2019-12-18 18:44 [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 3/3] clk: tegra20/30: Explicitly set parent clock for Video Decoder Dmitry Osipenko @ 2020-01-10 14:52 ` Thierry Reding 2 siblings, 0 replies; 5+ messages in thread From: Thierry Reding @ 2020-01-10 14:52 UTC (permalink / raw) To: Dmitry Osipenko Cc: Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad, Michael Turquette, Stephen Boyd, linux-tegra, linux-clk, linux-kernel [-- Attachment #1: Type: text/plain, Size: 652 bytes --] On Wed, Dec 18, 2019 at 09:44:05PM +0300, Dmitry Osipenko wrote: > UART clock is divided using divisor values from DLM/DLL registers when > enable-bit is unset in clk register and clk's divider configuration isn't > taken onto account in this case. This doesn't cause any problems, but > let's add a check for the divider's enable-bit state, for consistency. > > Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/clk/tegra/clk-divider.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) All three patches applied to for-5.6/clk, thanks. Thierry [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-01-10 14:52 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-12-18 18:44 [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 2/3] clk: tegra20/30: Don't pre-initialize displays parent clock Dmitry Osipenko 2020-01-07 23:21 ` Dmitry Osipenko 2019-12-18 18:44 ` [PATCH RESEND for 5.6 v1 3/3] clk: tegra20/30: Explicitly set parent clock for Video Decoder Dmitry Osipenko 2020-01-10 14:52 ` [PATCH RESEND for 5.6 v1 1/3] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Thierry Reding
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