* [PATCH v2 0/3] Add functions to operate USB PHY related clock.
@ 2020-06-28 17:15 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-28 17:15 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
v1->v2:
1.Use "WARN()" instead "BUG()".
2.Move the reformat part ot the new patch.
3.Remove unnecessary get_parent/set_parent functions.
周琰杰 (Zhou Yanjie) (3):
clk: JZ4780: Add functions for enable and disable USB PHY.
clk: JZ4780: Reformat the code to align it.
clk: X1000: Add support for calculat REFCLK of USB PHY.
drivers/clk/ingenic/jz4780-cgu.c | 155 ++++++++++++++++++++-------------------
drivers/clk/ingenic/x1000-cgu.c | 85 ++++++++++++++++++++-
2 files changed, 165 insertions(+), 75 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY.
2020-06-28 17:15 [PATCH v2 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
@ 2020-06-28 17:15 ` 周琰杰 (Zhou Yanjie)
2020-06-29 9:28 ` kernel test robot
2020-06-28 17:15 ` [PATCH v2 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2 siblings, 1 reply; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-28 17:15 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Add new functions to "jz4780_otg_phy_ops" to enable or disable the
USB PHY in the JZ4780 SoC.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
1.Use "WARN()" instead "BUG()".
2.Move the reformat part ot the new patch.
3.Remove unnecessary get_parent/set_parent functions.
drivers/clk/ingenic/jz4780-cgu.c | 67 ++++++++++++++++++++++------------------
1 file changed, 37 insertions(+), 30 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8a..e2e43bfe9697 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -4,6 +4,7 @@
*
* Copyright (c) 2013-2015 Imagination Technologies
* Author: Paul Burton <paul.burton@mips.com>
+ * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk-provider.h>
@@ -59,6 +60,7 @@
#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
#define USBPCR_OTGTUNE_MASK (0x7 << 14)
@@ -68,6 +70,7 @@
#define USBPCR_TXHSXVTUNE_MASK (0x3 << 4)
#define USBPCR_TXVREFTUNE_MASK 0xf
+
/* bits within the USBPCR1 register */
#define USBPCR1_REFCLKSEL_SHIFT 26
#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
@@ -100,32 +103,6 @@
static struct ingenic_cgu *cgu;
-static u8 jz4780_otg_phy_get_parent(struct clk_hw *hw)
-{
- /* we only use CLKCORE, revisit if that ever changes */
- return 0;
-}
-
-static int jz4780_otg_phy_set_parent(struct clk_hw *hw, u8 idx)
-{
- unsigned long flags;
- u32 usbpcr1;
-
- if (idx > 0)
- return -EINVAL;
-
- spin_lock_irqsave(&cgu->lock, flags);
-
- usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
- usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;
- /* we only use CLKCORE */
- usbpcr1 |= USBPCR1_REFCLKSEL_CORE;
- writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
-
- spin_unlock_irqrestore(&cgu->lock, flags);
- return 0;
-}
-
static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -149,7 +126,7 @@ static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
return 19200000;
}
- BUG();
+ WARN();
return parent_rate;
}
@@ -206,13 +183,43 @@ static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
return 0;
}
-static const struct clk_ops jz4780_otg_phy_ops = {
- .get_parent = jz4780_otg_phy_get_parent,
- .set_parent = jz4780_otg_phy_set_parent,
+static int jz4780_otg_phy_enable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+
+ writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
+ writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
+ return 0;
+}
+
+static void jz4780_otg_phy_disable(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+ writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
+ writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
+}
+
+static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
+{
+ void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
+ void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
+
+ return (readl(reg_opcr) & OPCR_SPENDN0) &&
+ !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
+ !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
+}
+
+static const struct clk_ops jz4780_otg_phy_ops = {
.recalc_rate = jz4780_otg_phy_recalc_rate,
.round_rate = jz4780_otg_phy_round_rate,
.set_rate = jz4780_otg_phy_set_rate,
+
+ .enable = jz4780_otg_phy_enable,
+ .disable = jz4780_otg_phy_disable,
+ .is_enabled = jz4780_otg_phy_is_enabled,
};
static int jz4780_core1_enable(struct clk_hw *hw)
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] clk: JZ4780: Reformat the code to align it.
2020-06-28 17:15 [PATCH v2 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
@ 2020-06-28 17:15 ` 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2 siblings, 0 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-28 17:15 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Reformat the code (add one level of indentation before the values),
to align the code in the macro definition section.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v2:
New patch.
drivers/clk/ingenic/jz4780-cgu.c | 90 ++++++++++++++++++++--------------------
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index e2e43bfe9697..20d6d5adfe8a 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -20,50 +20,50 @@
/* CGU register offsets */
#define CGU_REG_CLOCKCONTROL 0x00
-#define CGU_REG_LCR 0x04
-#define CGU_REG_APLL 0x10
-#define CGU_REG_MPLL 0x14
-#define CGU_REG_EPLL 0x18
-#define CGU_REG_VPLL 0x1c
-#define CGU_REG_CLKGR0 0x20
-#define CGU_REG_OPCR 0x24
-#define CGU_REG_CLKGR1 0x28
-#define CGU_REG_DDRCDR 0x2c
-#define CGU_REG_VPUCDR 0x30
-#define CGU_REG_USBPCR 0x3c
-#define CGU_REG_USBRDT 0x40
-#define CGU_REG_USBVBFIL 0x44
-#define CGU_REG_USBPCR1 0x48
-#define CGU_REG_LP0CDR 0x54
-#define CGU_REG_I2SCDR 0x60
-#define CGU_REG_LP1CDR 0x64
-#define CGU_REG_MSC0CDR 0x68
-#define CGU_REG_UHCCDR 0x6c
-#define CGU_REG_SSICDR 0x74
-#define CGU_REG_CIMCDR 0x7c
-#define CGU_REG_PCMCDR 0x84
-#define CGU_REG_GPUCDR 0x88
-#define CGU_REG_HDMICDR 0x8c
-#define CGU_REG_MSC1CDR 0xa4
-#define CGU_REG_MSC2CDR 0xa8
-#define CGU_REG_BCHCDR 0xac
-#define CGU_REG_CLOCKSTATUS 0xd4
+#define CGU_REG_LCR 0x04
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_EPLL 0x18
+#define CGU_REG_VPLL 0x1c
+#define CGU_REG_CLKGR0 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_CLKGR1 0x28
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_VPUCDR 0x30
+#define CGU_REG_USBPCR 0x3c
+#define CGU_REG_USBRDT 0x40
+#define CGU_REG_USBVBFIL 0x44
+#define CGU_REG_USBPCR1 0x48
+#define CGU_REG_LP0CDR 0x54
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LP1CDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_UHCCDR 0x6c
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_GPUCDR 0x88
+#define CGU_REG_HDMICDR 0x8c
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_MSC2CDR 0xa8
+#define CGU_REG_BCHCDR 0xac
+#define CGU_REG_CLOCKSTATUS 0xd4
/* bits within the OPCR register */
-#define OPCR_SPENDN0 BIT(7)
-#define OPCR_SPENDN1 BIT(6)
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
/* bits within the USBPCR register */
-#define USBPCR_USB_MODE BIT(31)
+#define USBPCR_USB_MODE BIT(31)
#define USBPCR_IDPULLUP_MASK (0x3 << 28)
-#define USBPCR_COMMONONN BIT(25)
-#define USBPCR_VBUSVLDEXT BIT(24)
+#define USBPCR_COMMONONN BIT(25)
+#define USBPCR_VBUSVLDEXT BIT(24)
#define USBPCR_VBUSVLDEXTSEL BIT(23)
-#define USBPCR_POR BIT(22)
-#define USBPCR_SIDDQ BIT(21)
-#define USBPCR_OTG_DISABLE BIT(20)
+#define USBPCR_POR BIT(22)
+#define USBPCR_SIDDQ BIT(21)
+#define USBPCR_OTG_DISABLE BIT(20)
#define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
-#define USBPCR_OTGTUNE_MASK (0x7 << 14)
+#define USBPCR_OTGTUNE_MASK (0x7 << 14)
#define USBPCR_SQRXTUNE_MASK (0x7 << 11)
#define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
#define USBPCR_TXPREEMPHTUNE BIT(6)
@@ -81,13 +81,13 @@
#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
-#define USBPCR1_USB_SEL BIT(28)
-#define USBPCR1_WORD_IF0 BIT(19)
-#define USBPCR1_WORD_IF1 BIT(18)
+#define USBPCR1_USB_SEL BIT(28)
+#define USBPCR1_WORD_IF0 BIT(19)
+#define USBPCR1_WORD_IF1 BIT(18)
/* bits within the USBRDT register */
-#define USBRDT_VBFIL_LD_EN BIT(25)
-#define USBRDT_USBRDT_MASK 0x7fffff
+#define USBRDT_VBFIL_LD_EN BIT(25)
+#define USBRDT_USBRDT_MASK 0x7fffff
/* bits within the USBVBFIL register */
#define USBVBFIL_IDDIGFIL_SHIFT 16
@@ -95,11 +95,11 @@
#define USBVBFIL_USBVBFIL_MASK (0xffff)
/* bits within the LCR register */
-#define LCR_PD_SCPU BIT(31)
-#define LCR_SCPUS BIT(27)
+#define LCR_PD_SCPU BIT(31)
+#define LCR_SCPUS BIT(27)
/* bits within the CLKGR1 register */
-#define CLKGR1_CORE1 BIT(15)
+#define CLKGR1_CORE1 BIT(15)
static struct ingenic_cgu *cgu;
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY.
2020-06-28 17:15 [PATCH v2 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
@ 2020-06-28 17:15 ` 周琰杰 (Zhou Yanjie)
2020-06-29 10:26 ` kernel test robot
2020-06-29 13:20 ` kernel test robot
2 siblings, 2 replies; 7+ messages in thread
From: 周琰杰 (Zhou Yanjie) @ 2020-06-28 17:15 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, sboyd, paul, mturquette, dongsheng.qiu, aric.pzqi,
rick.tyliu, yanfei.li, sernia.zhou, zhenwenjin
Add functions for calculat the rate of REFCLK, which is needed by
USB PHY in Ingenic X1000 SoC.
Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
1.Use "WARN()" instead "BUG()".
2.Remove unnecessary get_parent/set_parent functions.
drivers/clk/ingenic/x1000-cgu.c | 85 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 84 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 453f3323cb99..aa043f3cf11f 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -48,8 +48,88 @@
#define USBPCR_SIDDQ BIT(21)
#define USBPCR_OTG_DISABLE BIT(20)
+/* bits within the USBPCR1 register */
+#define USBPCR1_REFCLKSEL_SHIFT 26
+#define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
+#define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
+#define USBPCR1_REFCLKDIV_SHIFT 24
+#define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
+#define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
+
static struct ingenic_cgu *cgu;
+static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ u32 usbpcr1;
+ unsigned refclk_div;
+
+ usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
+ refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
+
+ switch (refclk_div) {
+ case USBPCR1_REFCLKDIV_12:
+ return 12000000;
+
+ case USBPCR1_REFCLKDIV_24:
+ return 48000000;
+
+ case USBPCR1_REFCLKDIV_48:
+ return 48000000;
+ }
+
+ WARN();
+ return parent_rate;
+}
+
+static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long *parent_rate)
+{
+ if (req_rate < 18000000)
+ return 12000000;
+
+ if (req_rate < 36000000)
+ return 24000000;
+
+ return 48000000;
+}
+
+static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
+ unsigned long parent_rate)
+{
+ unsigned long flags;
+ u32 usbpcr1, div_bits;
+
+ switch (req_rate) {
+ case 18000000:
+ div_bits = USBPCR1_REFCLKDIV_12;
+ break;
+
+ case 24000000:
+ div_bits = USBPCR1_REFCLKDIV_24;
+ break;
+
+ case 48000000:
+ div_bits = USBPCR1_REFCLKDIV_48;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&cgu->lock, flags);
+
+ usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
+ usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
+ usbpcr1 |= div_bits;
+ writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
+
+ spin_unlock_irqrestore(&cgu->lock, flags);
+ return 0;
+}
+
static int x1000_usb_phy_enable(struct clk_hw *hw)
{
void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
@@ -80,6 +160,10 @@ static int x1000_usb_phy_is_enabled(struct clk_hw *hw)
}
static const struct clk_ops x1000_otg_phy_ops = {
+ .recalc_rate = x1000_otg_phy_recalc_rate,
+ .round_rate = x1000_otg_phy_round_rate,
+ .set_rate = x1000_otg_phy_set_rate,
+
.enable = x1000_usb_phy_enable,
.disable = x1000_usb_phy_disable,
.is_enabled = x1000_usb_phy_is_enabled,
@@ -144,7 +228,6 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
},
},
-
/* Custom (SoC-specific) OTG PHY */
[X1000_CLK_OTGPHY] = {
--
2.11.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY.
2020-06-28 17:15 ` [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
@ 2020-06-29 9:28 ` kernel test robot
0 siblings, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-06-29 9:28 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), linux-clk
Cc: kbuild-all, linux-kernel, sboyd, paul, mturquette, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou
[-- Attachment #1: Type: text/plain, Size: 3497 bytes --]
Hi "周琰杰,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on linux/master linus/master v5.8-rc3 next-20200629]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-functions-to-operate-USB-PHY-related-clock/20200629-011858
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=alpha
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
In file included from arch/alpha/include/asm/bug.h:23,
from include/linux/bug.h:5,
from include/linux/thread_info.h:12,
from include/asm-generic/current.h:5,
from ./arch/alpha/include/generated/asm/current.h:1,
from include/linux/mutex.h:14,
from include/linux/kernfs.h:12,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clk-provider.h:9,
from drivers/clk/ingenic/jz4780-cgu.c:10:
drivers/clk/ingenic/jz4780-cgu.c: In function 'jz4780_otg_phy_recalc_rate':
>> include/asm-generic/bug.h:127:34: error: expected expression before ')' token
127 | int __ret_warn_on = !!(condition); \
| ^
>> drivers/clk/ingenic/jz4780-cgu.c:129:2: note: in expansion of macro 'WARN'
129 | WARN();
| ^~~~
include/asm-generic/bug.h:88:51: error: expected expression before ')' token
88 | warn_slowpath_fmt(__FILE__, __LINE__, taint, arg); \
| ^
include/asm-generic/bug.h:129:3: note: in expansion of macro '__WARN_printf'
129 | __WARN_printf(TAINT_WARN, format); \
| ^~~~~~~~~~~~~
>> drivers/clk/ingenic/jz4780-cgu.c:129:2: note: in expansion of macro 'WARN'
129 | WARN();
| ^~~~
vim +/WARN +129 drivers/clk/ingenic/jz4780-cgu.c
105
106 static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
107 unsigned long parent_rate)
108 {
109 u32 usbpcr1;
110 unsigned refclk_div;
111
112 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
113 refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
114
115 switch (refclk_div) {
116 case USBPCR1_REFCLKDIV_12:
117 return 12000000;
118
119 case USBPCR1_REFCLKDIV_24:
120 return 24000000;
121
122 case USBPCR1_REFCLKDIV_48:
123 return 48000000;
124
125 case USBPCR1_REFCLKDIV_19_2:
126 return 19200000;
127 }
128
> 129 WARN();
130 return parent_rate;
131 }
132
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65024 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY.
2020-06-28 17:15 ` [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
@ 2020-06-29 10:26 ` kernel test robot
2020-06-29 13:20 ` kernel test robot
1 sibling, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-06-29 10:26 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), linux-clk
Cc: kbuild-all, linux-kernel, sboyd, paul, mturquette, dongsheng.qiu,
aric.pzqi, rick.tyliu, yanfei.li, sernia.zhou
[-- Attachment #1: Type: text/plain, Size: 3417 bytes --]
Hi "周琰杰,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on clk/clk-next]
[also build test WARNING on linux/master linus/master v5.8-rc3 next-20200629]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-functions-to-operate-USB-PHY-related-clock/20200629-011858
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: alpha-allyesconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=alpha
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from arch/alpha/include/asm/bug.h:23,
from include/linux/bug.h:5,
from include/linux/thread_info.h:12,
from include/asm-generic/current.h:5,
from ./arch/alpha/include/generated/asm/current.h:1,
from include/linux/mutex.h:14,
from include/linux/kernfs.h:12,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clk-provider.h:9,
from drivers/clk/ingenic/x1000-cgu.c:7:
drivers/clk/ingenic/x1000-cgu.c: In function 'x1000_otg_phy_recalc_rate':
include/asm-generic/bug.h:127:34: error: expected expression before ')' token
127 | int __ret_warn_on = !!(condition); \
| ^
>> drivers/clk/ingenic/x1000-cgu.c:83:2: note: in expansion of macro 'WARN'
83 | WARN();
| ^~~~
include/asm-generic/bug.h:88:51: error: expected expression before ')' token
88 | warn_slowpath_fmt(__FILE__, __LINE__, taint, arg); \
| ^
include/asm-generic/bug.h:129:3: note: in expansion of macro '__WARN_printf'
129 | __WARN_printf(TAINT_WARN, format); \
| ^~~~~~~~~~~~~
>> drivers/clk/ingenic/x1000-cgu.c:83:2: note: in expansion of macro 'WARN'
83 | WARN();
| ^~~~
vim +/WARN +83 drivers/clk/ingenic/x1000-cgu.c
62
63 static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
64 unsigned long parent_rate)
65 {
66 u32 usbpcr1;
67 unsigned refclk_div;
68
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
70 refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
71
72 switch (refclk_div) {
73 case USBPCR1_REFCLKDIV_12:
74 return 12000000;
75
76 case USBPCR1_REFCLKDIV_24:
77 return 48000000;
78
79 case USBPCR1_REFCLKDIV_48:
80 return 48000000;
81 }
82
> 83 WARN();
84 return parent_rate;
85 }
86
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65024 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY.
2020-06-28 17:15 ` [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2020-06-29 10:26 ` kernel test robot
@ 2020-06-29 13:20 ` kernel test robot
1 sibling, 0 replies; 7+ messages in thread
From: kernel test robot @ 2020-06-29 13:20 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), linux-clk
Cc: kbuild-all, clang-built-linux, linux-kernel, sboyd, paul,
mturquette, dongsheng.qiu, aric.pzqi, rick.tyliu, yanfei.li,
sernia.zhou
[-- Attachment #1: Type: text/plain, Size: 2847 bytes --]
Hi "周琰杰,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on linux/master linus/master v5.8-rc3 next-20200629]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Add-functions-to-operate-USB-PHY-related-clock/20200629-011858
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: mips-randconfig-r012-20200629 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project a28d38a6bca1726d56c9b373f4c7dc5264fc7716)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mips-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/clk/ingenic/x1000-cgu.c:83:2: error: expected expression
WARN();
^
include/asm-generic/bug.h:127:34: note: expanded from macro 'WARN'
int __ret_warn_on = !!(condition); \
^
>> drivers/clk/ingenic/x1000-cgu.c:83:2: error: expected expression
include/asm-generic/bug.h:129:3: note: expanded from macro 'WARN'
__WARN_printf(TAINT_WARN, format); \
^
include/asm-generic/bug.h:88:51: note: expanded from macro '__WARN_printf'
warn_slowpath_fmt(__FILE__, __LINE__, taint, arg); \
^
2 errors generated.
vim +83 drivers/clk/ingenic/x1000-cgu.c
62
63 static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw,
64 unsigned long parent_rate)
65 {
66 u32 usbpcr1;
67 unsigned refclk_div;
68
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
70 refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
71
72 switch (refclk_div) {
73 case USBPCR1_REFCLKDIV_12:
74 return 12000000;
75
76 case USBPCR1_REFCLKDIV_24:
77 return 48000000;
78
79 case USBPCR1_REFCLKDIV_48:
80 return 48000000;
81 }
82
> 83 WARN();
84 return parent_rate;
85 }
86
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 31039 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-06-29 19:56 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-28 17:15 [PATCH v2 0/3] Add functions to operate USB PHY related clock 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 1/3] clk: JZ4780: Add functions for enable and disable USB PHY 周琰杰 (Zhou Yanjie)
2020-06-29 9:28 ` kernel test robot
2020-06-28 17:15 ` [PATCH v2 2/3] clk: JZ4780: Reformat the code to align it 周琰杰 (Zhou Yanjie)
2020-06-28 17:15 ` [PATCH v2 3/3] clk: X1000: Add support for calculat REFCLK of USB PHY 周琰杰 (Zhou Yanjie)
2020-06-29 10:26 ` kernel test robot
2020-06-29 13:20 ` kernel test robot
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).