From: Dave Hansen <dave.hansen@intel.com>
To: "Dey, Megha" <megha.dey@intel.com>, Andy Lutomirski <luto@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>,
Asit K Mallick <asit.k.mallick@intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Linux Crypto Mailing List <linux-crypto@vger.kernel.org>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S. Miller" <davem@davemloft.net>,
"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
"Chen, Tim C" <tim.c.chen@intel.com>,
"Kleen, Andi" <andi.kleen@intel.com>,
greg.b.tucker@intel.com, "Kasten,
Robert A" <robert.a.kasten@intel.com>,
rajendrakumar.chinnaiyan@intel.com, tomasz.kantecki@intel.com,
ryan.d.saffores@intel.com, ilya.albrekht@intel.com,
Kyung Min Park <kyung.min.park@intel.com>,
Weiny Ira <ira.weiny@intel.com>,
Eric Biggers <ebiggers@kernel.org>,
Ard Biesheuvel <ardb@kernel.org>, X86 ML <x86@kernel.org>
Subject: Re: [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms
Date: Mon, 31 Jan 2022 11:18:50 -0800 [thread overview]
Message-ID: <0a10e16b-df77-9a7f-6964-8dc3e114b30b@intel.com> (raw)
In-Reply-To: <e8ce1146-3952-6977-1d0e-a22758e58914@intel.com>
On 1/31/22 10:43, Dey, Megha wrote:
> With this implementation, we see a 1.5X improvement on ICX/ICL for 16KB
> buffers compared to the existing kernel AES-GCM implementation that
> works on 128-bit XMM registers.
What is your best guess about how future-proof this implementation is?
Will this be an ICL/ICX one-off? Or, will implementations using 256-bit
YMM registers continue to enjoy a frequency advantage over the 512-bit
implementations for a long time?
next prev parent reply other threads:[~2022-01-31 19:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-23 7:28 [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms Megha Dey
2021-01-23 7:28 ` [RFC V2 1/5] crypto: aesni - fix coding style for if/else block Megha Dey
2021-01-23 7:28 ` [RFC V2 2/5] x86: Probe assembler capabilities for VAES and VPLCMULQDQ support Megha Dey
2021-01-23 7:28 ` [RFC V2 3/5] crypto: crct10dif - Accelerated CRC T10 DIF with vectorized instruction Megha Dey
2021-01-23 7:28 ` [RFC V2 4/5] crypto: aesni - AES CTR x86_64 "by16" AVX512 optimization Megha Dey
2021-01-23 7:28 ` [RFC V2 5/5] crypto: aesni - AVX512 version of AESNI-GCM using VPCLMULQDQ Megha Dey
2021-01-24 16:23 ` [RFC V2 0/5] Introduce AVX512 optimized crypto algorithms Andy Lutomirski
2021-02-24 0:54 ` Dey, Megha
2021-02-24 17:42 ` Andy Lutomirski
2022-01-31 18:43 ` Dey, Megha
2022-01-31 19:18 ` Dave Hansen [this message]
2022-02-01 16:42 ` Dey, Megha
2022-02-24 19:31 ` Dey, Megha
2022-03-05 18:37 ` Andy Lutomirski
2021-05-07 16:22 ` Dave Hansen
2021-01-25 17:27 ` Dave Hansen
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