* [PATCH 0/4] crypto: hisilicon: misc sgl fixes
@ 2019-09-30 7:08 Zhou Wang
2019-09-30 7:08 ` [PATCH 1/4] crypto: hisilicon - merge sgl support to hisi_qm module Zhou Wang
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Zhou Wang @ 2019-09-30 7:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm, Zhou Wang
This series fixes some preblems in sgl code. The main change is merging sgl
code into hisi_qm module.
These problem are also fixed:
- Let user driver to pass the configure of sge number in one sgl when
creating hardware sgl resources.
- When disabling SMMU, it may fail to allocate large continuous memory. We
fixes this by allocating memory by blocks.
This series is based on Arnd's patch: https://lkml.org/lkml/2019/9/19/455
Shunkun Tan (1):
crypto: hisilicon - add sgl_sge_nr module param for zip
Zhou Wang (3):
crypto: hisilicon - merge sgl support to hisi_qm module
crypto: hisilicon - fix large sgl memory allocation problem when
disable smmu
crypto: hisilicon - misc fix about sgl
MAINTAINERS | 1 -
drivers/crypto/hisilicon/Kconfig | 9 --
drivers/crypto/hisilicon/Makefile | 4 +-
drivers/crypto/hisilicon/qm.h | 13 +++
drivers/crypto/hisilicon/sgl.c | 182 +++++++++++++++++++-----------
drivers/crypto/hisilicon/sgl.h | 24 ----
drivers/crypto/hisilicon/zip/zip.h | 1 -
drivers/crypto/hisilicon/zip/zip_crypto.c | 44 ++++++--
8 files changed, 167 insertions(+), 111 deletions(-)
delete mode 100644 drivers/crypto/hisilicon/sgl.h
--
2.8.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/4] crypto: hisilicon - merge sgl support to hisi_qm module
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
@ 2019-09-30 7:08 ` Zhou Wang
2019-09-30 7:08 ` [PATCH 2/4] crypto: hisilicon - add sgl_sge_nr module param for zip Zhou Wang
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-09-30 7:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm, Zhou Wang, Shukun Tan
As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into
qm module and rename it as hisi_qm, which reduces the number of module and
make the name less generic.
This patch also modify the interface of SGL:
- Create/free hisi_acc_sgl_pool inside.
- Let user to pass the SGE number in one SGL when creating sgl pool, which
is better than a unified module parameter for sgl module before.
- Modify zip driver according to sgl interface change.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
---
MAINTAINERS | 1 -
drivers/crypto/hisilicon/Kconfig | 9 ----
drivers/crypto/hisilicon/Makefile | 4 +-
drivers/crypto/hisilicon/qm.h | 11 +++++
drivers/crypto/hisilicon/sgl.c | 73 ++++++++++++++-----------------
drivers/crypto/hisilicon/sgl.h | 24 ----------
drivers/crypto/hisilicon/zip/zip.h | 1 -
drivers/crypto/hisilicon/zip/zip_crypto.c | 20 +++++----
8 files changed, 58 insertions(+), 85 deletions(-)
delete mode 100644 drivers/crypto/hisilicon/sgl.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a97f1be..8671e1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7417,7 +7417,6 @@ S: Maintained
F: drivers/crypto/hisilicon/qm.c
F: drivers/crypto/hisilicon/qm.h
F: drivers/crypto/hisilicon/sgl.c
-F: drivers/crypto/hisilicon/sgl.h
F: drivers/crypto/hisilicon/zip/
F: Documentation/ABI/testing/debugfs-hisi-zip
diff --git a/drivers/crypto/hisilicon/Kconfig b/drivers/crypto/hisilicon/Kconfig
index 7bfcaa7..79c82ba 100644
--- a/drivers/crypto/hisilicon/Kconfig
+++ b/drivers/crypto/hisilicon/Kconfig
@@ -22,21 +22,12 @@ config CRYPTO_DEV_HISI_QM
HiSilicon accelerator engines use a common queue management
interface. Specific engine driver may use this module.
-config CRYPTO_HISI_SGL
- tristate
- depends on ARM64 || COMPILE_TEST
- help
- HiSilicon accelerator engines use a common hardware scatterlist
- interface for data format. Specific engine driver may use this
- module.
-
config CRYPTO_DEV_HISI_ZIP
tristate "Support for HiSilicon ZIP accelerator"
depends on PCI && PCI_MSI
depends on ARM64 || (COMPILE_TEST && 64BIT)
depends on !CPU_BIG_ENDIAN || COMPILE_TEST
select CRYPTO_DEV_HISI_QM
- select CRYPTO_HISI_SGL
select SG_SPLIT
help
Support for HiSilicon ZIP Driver
diff --git a/drivers/crypto/hisilicon/Makefile b/drivers/crypto/hisilicon/Makefile
index 45a2797..4978d14 100644
--- a/drivers/crypto/hisilicon/Makefile
+++ b/drivers/crypto/hisilicon/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_HISI_SEC) += sec/
-obj-$(CONFIG_CRYPTO_DEV_HISI_QM) += qm.o
-obj-$(CONFIG_CRYPTO_HISI_SGL) += sgl.o
+obj-$(CONFIG_CRYPTO_DEV_HISI_QM) += hisi_qm.o
+hisi_qm-objs = qm.o sgl.o
obj-$(CONFIG_CRYPTO_DEV_HISI_ZIP) += zip/
diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h
index 70e672ae..978d2ae 100644
--- a/drivers/crypto/hisilicon/qm.h
+++ b/drivers/crypto/hisilicon/qm.h
@@ -212,4 +212,15 @@ void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
int hisi_qm_hw_error_handle(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
+
+struct hisi_acc_sgl_pool;
+struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
+ struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
+ u32 index, dma_addr_t *hw_sgl_dma);
+void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
+ struct hisi_acc_hw_sgl *hw_sgl);
+struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
+ u32 count, u32 sge_nr);
+void hisi_acc_free_sgl_pool(struct device *dev,
+ struct hisi_acc_sgl_pool *pool);
#endif
diff --git a/drivers/crypto/hisilicon/sgl.c b/drivers/crypto/hisilicon/sgl.c
index e083d17..81a9040 100644
--- a/drivers/crypto/hisilicon/sgl.c
+++ b/drivers/crypto/hisilicon/sgl.c
@@ -2,38 +2,13 @@
/* Copyright (c) 2019 HiSilicon Limited. */
#include <linux/dma-mapping.h>
#include <linux/module.h>
-#include "./sgl.h"
+#include <linux/slab.h>
#define HISI_ACC_SGL_SGE_NR_MIN 1
#define HISI_ACC_SGL_SGE_NR_MAX 255
-#define HISI_ACC_SGL_SGE_NR_DEF 10
#define HISI_ACC_SGL_NR_MAX 256
#define HISI_ACC_SGL_ALIGN_SIZE 64
-static int acc_sgl_sge_set(const char *val, const struct kernel_param *kp)
-{
- int ret;
- u32 n;
-
- if (!val)
- return -EINVAL;
-
- ret = kstrtou32(val, 10, &n);
- if (ret != 0 || n > HISI_ACC_SGL_SGE_NR_MAX || n == 0)
- return -EINVAL;
-
- return param_set_int(val, kp);
-}
-
-static const struct kernel_param_ops acc_sgl_sge_ops = {
- .set = acc_sgl_sge_set,
- .get = param_get_int,
-};
-
-static u32 acc_sgl_sge_nr = HISI_ACC_SGL_SGE_NR_DEF;
-module_param_cb(acc_sgl_sge_nr, &acc_sgl_sge_ops, &acc_sgl_sge_nr, 0444);
-MODULE_PARM_DESC(acc_sgl_sge_nr, "Number of sge in sgl(1-255)");
-
struct acc_hw_sge {
dma_addr_t buf;
void *page_ctrl;
@@ -55,37 +30,54 @@ struct hisi_acc_hw_sgl {
struct acc_hw_sge sge_entries[];
} __aligned(1);
+struct hisi_acc_sgl_pool {
+ struct hisi_acc_hw_sgl *sgl;
+ dma_addr_t sgl_dma;
+ size_t size;
+ u32 count;
+ u32 sge_nr;
+ size_t sgl_size;
+};
+
/**
* hisi_acc_create_sgl_pool() - Create a hw sgl pool.
* @dev: The device which hw sgl pool belongs to.
- * @pool: Pointer of pool.
* @count: Count of hisi_acc_hw_sgl in pool.
+ * @sge_nr: The count of sge in hw_sgl
*
* This function creates a hw sgl pool, after this user can get hw sgl memory
* from it.
*/
-int hisi_acc_create_sgl_pool(struct device *dev,
- struct hisi_acc_sgl_pool *pool, u32 count)
+struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
+ u32 count, u32 sge_nr)
{
+ struct hisi_acc_sgl_pool *pool;
u32 sgl_size;
u32 size;
- if (!dev || !pool || !count)
- return -EINVAL;
+ if (!dev || !count || !sge_nr || sge_nr > HISI_ACC_SGL_SGE_NR_MAX)
+ return ERR_PTR(-EINVAL);
- sgl_size = sizeof(struct acc_hw_sge) * acc_sgl_sge_nr +
+ sgl_size = sizeof(struct acc_hw_sge) * sge_nr +
sizeof(struct hisi_acc_hw_sgl);
size = sgl_size * count;
+ pool = kzalloc(sizeof(*pool), GFP_KERNEL);
+ if (!pool)
+ return ERR_PTR(-ENOMEM);
+
pool->sgl = dma_alloc_coherent(dev, size, &pool->sgl_dma, GFP_KERNEL);
- if (!pool->sgl)
- return -ENOMEM;
+ if (!pool->sgl) {
+ kfree(pool);
+ return ERR_PTR(-ENOMEM);
+ }
pool->size = size;
pool->count = count;
pool->sgl_size = sgl_size;
+ pool->sge_nr = sge_nr;
- return 0;
+ return pool;
}
EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
@@ -98,8 +90,11 @@ EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
*/
void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)
{
+ if (!dev || !pool)
+ return;
+
dma_free_coherent(dev, pool->size, pool->sgl, pool->sgl_dma);
- memset(pool, 0, sizeof(struct hisi_acc_sgl_pool));
+ kfree(pool);
}
EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
@@ -156,7 +151,7 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
int sg_n = sg_nents(sgl);
int i, ret;
- if (!dev || !sgl || !pool || !hw_sgl_dma || sg_n > acc_sgl_sge_nr)
+ if (!dev || !sgl || !pool || !hw_sgl_dma || sg_n > pool->sge_nr)
return ERR_PTR(-EINVAL);
ret = dma_map_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
@@ -168,7 +163,7 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
ret = -ENOMEM;
goto err_unmap_sg;
}
- curr_hw_sgl->entry_length_in_sgl = acc_sgl_sge_nr;
+ curr_hw_sgl->entry_length_in_sgl = pool->sge_nr;
curr_hw_sge = curr_hw_sgl->sge_entries;
for_each_sg(sgl, sg, sg_n, i) {
@@ -177,7 +172,7 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
curr_hw_sge++;
}
- update_hw_sgl_sum_sge(curr_hw_sgl, acc_sgl_sge_nr);
+ update_hw_sgl_sum_sge(curr_hw_sgl, pool->sge_nr);
*hw_sgl_dma = curr_sgl_dma;
return curr_hw_sgl;
diff --git a/drivers/crypto/hisilicon/sgl.h b/drivers/crypto/hisilicon/sgl.h
deleted file mode 100644
index 3ac8871..0000000
--- a/drivers/crypto/hisilicon/sgl.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Copyright (c) 2019 HiSilicon Limited. */
-#ifndef HISI_ACC_SGL_H
-#define HISI_ACC_SGL_H
-
-struct hisi_acc_sgl_pool {
- struct hisi_acc_hw_sgl *sgl;
- dma_addr_t sgl_dma;
- size_t size;
- u32 count;
- size_t sgl_size;
-};
-
-struct hisi_acc_hw_sgl *
-hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
- struct scatterlist *sgl,
- struct hisi_acc_sgl_pool *pool,
- u32 index, dma_addr_t *hw_sgl_dma);
-void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
- struct hisi_acc_hw_sgl *hw_sgl);
-int hisi_acc_create_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool,
- u32 count);
-void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool);
-#endif
diff --git a/drivers/crypto/hisilicon/zip/zip.h b/drivers/crypto/hisilicon/zip/zip.h
index ffb00d9..79fc4dd 100644
--- a/drivers/crypto/hisilicon/zip/zip.h
+++ b/drivers/crypto/hisilicon/zip/zip.h
@@ -8,7 +8,6 @@
#include <linux/list.h>
#include "../qm.h"
-#include "../sgl.h"
/* hisi_zip_sqe dw3 */
#define HZIP_BD_STATUS_M GENMASK(7, 0)
diff --git a/drivers/crypto/hisilicon/zip/zip_crypto.c b/drivers/crypto/hisilicon/zip/zip_crypto.c
index 5902354..a82bee5 100644
--- a/drivers/crypto/hisilicon/zip/zip_crypto.c
+++ b/drivers/crypto/hisilicon/zip/zip_crypto.c
@@ -22,6 +22,7 @@
#define HZIP_CTX_Q_NUM 2
#define HZIP_GZIP_HEAD_BUF 256
#define HZIP_ALG_PRIORITY 300
+#define HZIP_SGL_SGE_NR 10
static const u8 zlib_head[HZIP_ZLIB_HEAD_SIZE] = {0x78, 0x9c};
static const u8 gzip_head[HZIP_GZIP_HEAD_SIZE] = {0x1f, 0x8b, 0x08, 0x0, 0x0,
@@ -67,7 +68,7 @@ struct hisi_zip_qp_ctx {
struct hisi_qp *qp;
struct hisi_zip_sqe zip_sqe;
struct hisi_zip_req_q req_q;
- struct hisi_acc_sgl_pool sgl_pool;
+ struct hisi_acc_sgl_pool *sgl_pool;
struct hisi_zip *zip_dev;
struct hisi_zip_ctx *ctx;
};
@@ -265,14 +266,15 @@ static void hisi_zip_release_req_q(struct hisi_zip_ctx *ctx)
static int hisi_zip_create_sgl_pool(struct hisi_zip_ctx *ctx)
{
struct hisi_zip_qp_ctx *tmp;
- int i, ret;
+ struct device *dev;
+ int i;
for (i = 0; i < HZIP_CTX_Q_NUM; i++) {
tmp = &ctx->qp_ctx[i];
- ret = hisi_acc_create_sgl_pool(&tmp->qp->qm->pdev->dev,
- &tmp->sgl_pool,
- QM_Q_DEPTH << 1);
- if (ret < 0) {
+ dev = &tmp->qp->qm->pdev->dev;
+ tmp->sgl_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH << 1,
+ HZIP_SGL_SGE_NR);
+ if (IS_ERR(tmp->sgl_pool)) {
if (i == 1)
goto err_free_sgl_pool0;
return -ENOMEM;
@@ -283,7 +285,7 @@ static int hisi_zip_create_sgl_pool(struct hisi_zip_ctx *ctx)
err_free_sgl_pool0:
hisi_acc_free_sgl_pool(&ctx->qp_ctx[QPC_COMP].qp->qm->pdev->dev,
- &ctx->qp_ctx[QPC_COMP].sgl_pool);
+ ctx->qp_ctx[QPC_COMP].sgl_pool);
return -ENOMEM;
}
@@ -293,7 +295,7 @@ static void hisi_zip_release_sgl_pool(struct hisi_zip_ctx *ctx)
for (i = 0; i < HZIP_CTX_Q_NUM; i++)
hisi_acc_free_sgl_pool(&ctx->qp_ctx[i].qp->qm->pdev->dev,
- &ctx->qp_ctx[i].sgl_pool);
+ ctx->qp_ctx[i].sgl_pool);
}
static void hisi_zip_remove_req(struct hisi_zip_qp_ctx *qp_ctx,
@@ -512,7 +514,7 @@ static int hisi_zip_do_work(struct hisi_zip_req *req,
struct hisi_zip_sqe *zip_sqe = &qp_ctx->zip_sqe;
struct hisi_qp *qp = qp_ctx->qp;
struct device *dev = &qp->qm->pdev->dev;
- struct hisi_acc_sgl_pool *pool = &qp_ctx->sgl_pool;
+ struct hisi_acc_sgl_pool *pool = qp_ctx->sgl_pool;
dma_addr_t input;
dma_addr_t output;
int ret;
--
2.8.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] crypto: hisilicon - add sgl_sge_nr module param for zip
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
2019-09-30 7:08 ` [PATCH 1/4] crypto: hisilicon - merge sgl support to hisi_qm module Zhou Wang
@ 2019-09-30 7:08 ` Zhou Wang
2019-09-30 7:08 ` [PATCH 3/4] crypto: hisilicon - fix large sgl memory allocation problem when disable smmu Zhou Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-09-30 7:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm, Shukun Tan, Zhou Wang
From: Shukun Tan <tanshukun1@huawei.com>
Add a module parameter for zip driver to set the number of SGE in one SGL.
Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
drivers/crypto/hisilicon/qm.h | 2 ++
drivers/crypto/hisilicon/sgl.c | 2 +-
drivers/crypto/hisilicon/zip/zip_crypto.c | 26 +++++++++++++++++++++++++-
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/hisilicon/qm.h b/drivers/crypto/hisilicon/qm.h
index 978d2ae..103e2fd 100644
--- a/drivers/crypto/hisilicon/qm.h
+++ b/drivers/crypto/hisilicon/qm.h
@@ -75,6 +75,8 @@
#define QM_Q_DEPTH 1024
+#define HISI_ACC_SGL_SGE_NR_MAX 255
+
enum qp_state {
QP_STOP,
};
diff --git a/drivers/crypto/hisilicon/sgl.c b/drivers/crypto/hisilicon/sgl.c
index 81a9040..f71de0d 100644
--- a/drivers/crypto/hisilicon/sgl.c
+++ b/drivers/crypto/hisilicon/sgl.c
@@ -3,9 +3,9 @@
#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/slab.h>
+#include "qm.h"
#define HISI_ACC_SGL_SGE_NR_MIN 1
-#define HISI_ACC_SGL_SGE_NR_MAX 255
#define HISI_ACC_SGL_NR_MAX 256
#define HISI_ACC_SGL_ALIGN_SIZE 64
diff --git a/drivers/crypto/hisilicon/zip/zip_crypto.c b/drivers/crypto/hisilicon/zip/zip_crypto.c
index a82bee5..9d31b80 100644
--- a/drivers/crypto/hisilicon/zip/zip_crypto.c
+++ b/drivers/crypto/hisilicon/zip/zip_crypto.c
@@ -79,6 +79,30 @@ struct hisi_zip_ctx {
struct hisi_zip_qp_ctx qp_ctx[HZIP_CTX_Q_NUM];
};
+static int sgl_sge_nr_set(const char *val, const struct kernel_param *kp)
+{
+ int ret;
+ u16 n;
+
+ if (!val)
+ return -EINVAL;
+
+ ret = kstrtou16(val, 10, &n);
+ if (ret || n == 0 || n > HISI_ACC_SGL_SGE_NR_MAX)
+ return -EINVAL;
+
+ return param_set_int(val, kp);
+}
+
+static const struct kernel_param_ops sgl_sge_nr_ops = {
+ .set = sgl_sge_nr_set,
+ .get = param_get_int,
+};
+
+static u16 sgl_sge_nr = HZIP_SGL_SGE_NR;
+module_param_cb(sgl_sge_nr, &sgl_sge_nr_ops, &sgl_sge_nr, 0444);
+MODULE_PARM_DESC(sgl_sge_nr, "Number of sge in sgl(1-255)");
+
static void hisi_zip_config_buf_type(struct hisi_zip_sqe *sqe, u8 buf_type)
{
u32 val;
@@ -273,7 +297,7 @@ static int hisi_zip_create_sgl_pool(struct hisi_zip_ctx *ctx)
tmp = &ctx->qp_ctx[i];
dev = &tmp->qp->qm->pdev->dev;
tmp->sgl_pool = hisi_acc_create_sgl_pool(dev, QM_Q_DEPTH << 1,
- HZIP_SGL_SGE_NR);
+ sgl_sge_nr);
if (IS_ERR(tmp->sgl_pool)) {
if (i == 1)
goto err_free_sgl_pool0;
--
2.8.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] crypto: hisilicon - fix large sgl memory allocation problem when disable smmu
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
2019-09-30 7:08 ` [PATCH 1/4] crypto: hisilicon - merge sgl support to hisi_qm module Zhou Wang
2019-09-30 7:08 ` [PATCH 2/4] crypto: hisilicon - add sgl_sge_nr module param for zip Zhou Wang
@ 2019-09-30 7:08 ` Zhou Wang
2019-09-30 7:08 ` [PATCH 4/4] crypto: hisilicon - misc fix about sgl Zhou Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-09-30 7:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm, Zhou Wang, Shukun Tan
When disabling SMMU, it may fail to allocate large continuous memory. This
patch fixes this by allocating memory as blocks.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
---
drivers/crypto/hisilicon/sgl.c | 83 ++++++++++++++++++++++++++++++++++--------
1 file changed, 68 insertions(+), 15 deletions(-)
diff --git a/drivers/crypto/hisilicon/sgl.c b/drivers/crypto/hisilicon/sgl.c
index f71de0d..f017361 100644
--- a/drivers/crypto/hisilicon/sgl.c
+++ b/drivers/crypto/hisilicon/sgl.c
@@ -8,6 +8,7 @@
#define HISI_ACC_SGL_SGE_NR_MIN 1
#define HISI_ACC_SGL_NR_MAX 256
#define HISI_ACC_SGL_ALIGN_SIZE 64
+#define HISI_ACC_MEM_BLOCK_NR 5
struct acc_hw_sge {
dma_addr_t buf;
@@ -31,9 +32,13 @@ struct hisi_acc_hw_sgl {
} __aligned(1);
struct hisi_acc_sgl_pool {
- struct hisi_acc_hw_sgl *sgl;
- dma_addr_t sgl_dma;
- size_t size;
+ struct mem_block {
+ struct hisi_acc_hw_sgl *sgl;
+ dma_addr_t sgl_dma;
+ size_t size;
+ } mem_block[HISI_ACC_MEM_BLOCK_NR];
+ u32 sgl_num_per_block;
+ u32 block_num;
u32 count;
u32 sge_nr;
size_t sgl_size;
@@ -51,33 +56,66 @@ struct hisi_acc_sgl_pool {
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
u32 count, u32 sge_nr)
{
+ u32 sgl_size, block_size, sgl_num_per_block, block_num, remain_sgl = 0;
struct hisi_acc_sgl_pool *pool;
- u32 sgl_size;
- u32 size;
+ struct mem_block *block;
+ u32 i, j;
if (!dev || !count || !sge_nr || sge_nr > HISI_ACC_SGL_SGE_NR_MAX)
return ERR_PTR(-EINVAL);
sgl_size = sizeof(struct acc_hw_sge) * sge_nr +
sizeof(struct hisi_acc_hw_sgl);
- size = sgl_size * count;
+ block_size = PAGE_SIZE * (1 << (MAX_ORDER - 1));
+ sgl_num_per_block = block_size / sgl_size;
+ block_num = count / sgl_num_per_block;
+ remain_sgl = count % sgl_num_per_block;
+
+ if ((!remain_sgl && block_num > HISI_ACC_MEM_BLOCK_NR) ||
+ (remain_sgl > 0 && block_num > HISI_ACC_MEM_BLOCK_NR - 1))
+ return ERR_PTR(-EINVAL);
pool = kzalloc(sizeof(*pool), GFP_KERNEL);
if (!pool)
return ERR_PTR(-ENOMEM);
+ block = pool->mem_block;
- pool->sgl = dma_alloc_coherent(dev, size, &pool->sgl_dma, GFP_KERNEL);
- if (!pool->sgl) {
- kfree(pool);
- return ERR_PTR(-ENOMEM);
+ for (i = 0; i < block_num; i++) {
+ block[i].sgl = dma_alloc_coherent(dev, block_size,
+ &block[i].sgl_dma,
+ GFP_KERNEL);
+ if (!block[i].sgl)
+ goto err_free_mem;
+
+ block[i].size = block_size;
}
- pool->size = size;
+ if (remain_sgl > 0) {
+ block[i].sgl = dma_alloc_coherent(dev, remain_sgl * sgl_size,
+ &block[i].sgl_dma,
+ GFP_KERNEL);
+ if (!block[i].sgl)
+ goto err_free_mem;
+
+ block[i].size = remain_sgl * sgl_size;
+ }
+
+ pool->sgl_num_per_block = sgl_num_per_block;
+ pool->block_num = remain_sgl ? block_num + 1 : block_num;
pool->count = count;
pool->sgl_size = sgl_size;
pool->sge_nr = sge_nr;
return pool;
+
+err_free_mem:
+ for (j = 0; j < i; j++) {
+ dma_free_coherent(dev, block_size, block[j].sgl,
+ block[j].sgl_dma);
+ memset(block + j, 0, sizeof(*block));
+ }
+ kfree(pool);
+ return ERR_PTR(-ENOMEM);
}
EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
@@ -90,10 +128,18 @@ EXPORT_SYMBOL_GPL(hisi_acc_create_sgl_pool);
*/
void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)
{
+ struct mem_block *block;
+ int i;
+
if (!dev || !pool)
return;
- dma_free_coherent(dev, pool->size, pool->sgl, pool->sgl_dma);
+ block = pool->mem_block;
+
+ for (i = 0; i < pool->block_num; i++)
+ dma_free_coherent(dev, block[i].size, block[i].sgl,
+ block[i].sgl_dma);
+
kfree(pool);
}
EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
@@ -101,11 +147,18 @@ EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool, u32 index,
dma_addr_t *hw_sgl_dma)
{
- if (!pool || !hw_sgl_dma || index >= pool->count || !pool->sgl)
+ struct mem_block *block;
+ u32 block_index, offset;
+
+ if (!pool || !hw_sgl_dma || index >= pool->count)
return ERR_PTR(-EINVAL);
- *hw_sgl_dma = pool->sgl_dma + pool->sgl_size * index;
- return (void *)pool->sgl + pool->sgl_size * index;
+ block = pool->mem_block;
+ block_index = index / pool->sgl_num_per_block;
+ offset = index % pool->sgl_num_per_block;
+
+ *hw_sgl_dma = block[block_index].sgl_dma + pool->sgl_size * offset;
+ return (void *)block[block_index].sgl + pool->sgl_size * offset;
}
void acc_put_sgl(struct hisi_acc_sgl_pool *pool, u32 index) {}
--
2.8.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] crypto: hisilicon - misc fix about sgl
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
` (2 preceding siblings ...)
2019-09-30 7:08 ` [PATCH 3/4] crypto: hisilicon - fix large sgl memory allocation problem when disable smmu Zhou Wang
@ 2019-09-30 7:08 ` Zhou Wang
2019-10-10 8:21 ` [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
2019-10-10 12:54 ` Herbert Xu
5 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-09-30 7:08 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm, Zhou Wang, Shukun Tan
This patch fixes some misc problems in sgl codes, e.g. missing static,
sparse error and input parameter check.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Shukun Tan <tanshukun1@huawei.com>
---
drivers/crypto/hisilicon/sgl.c | 40 ++++++++++++++++++++++------------------
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/drivers/crypto/hisilicon/sgl.c b/drivers/crypto/hisilicon/sgl.c
index f017361..bf72603 100644
--- a/drivers/crypto/hisilicon/sgl.c
+++ b/drivers/crypto/hisilicon/sgl.c
@@ -144,8 +144,8 @@ void hisi_acc_free_sgl_pool(struct device *dev, struct hisi_acc_sgl_pool *pool)
}
EXPORT_SYMBOL_GPL(hisi_acc_free_sgl_pool);
-struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool, u32 index,
- dma_addr_t *hw_sgl_dma)
+static struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool,
+ u32 index, dma_addr_t *hw_sgl_dma)
{
struct mem_block *block;
u32 block_index, offset;
@@ -161,23 +161,24 @@ struct hisi_acc_hw_sgl *acc_get_sgl(struct hisi_acc_sgl_pool *pool, u32 index,
return (void *)block[block_index].sgl + pool->sgl_size * offset;
}
-void acc_put_sgl(struct hisi_acc_sgl_pool *pool, u32 index) {}
-
static void sg_map_to_hw_sg(struct scatterlist *sgl,
struct acc_hw_sge *hw_sge)
{
hw_sge->buf = sgl->dma_address;
- hw_sge->len = sgl->dma_length;
+ hw_sge->len = cpu_to_le32(sgl->dma_length);
}
static void inc_hw_sgl_sge(struct hisi_acc_hw_sgl *hw_sgl)
{
- hw_sgl->entry_sum_in_sgl++;
+ u16 var = le16_to_cpu(hw_sgl->entry_sum_in_sgl);
+
+ var++;
+ hw_sgl->entry_sum_in_sgl = cpu_to_le16(var);
}
static void update_hw_sgl_sum_sge(struct hisi_acc_hw_sgl *hw_sgl, u16 sum)
{
- hw_sgl->entry_sum_in_chain = sum;
+ hw_sgl->entry_sum_in_chain = cpu_to_le16(sum);
}
/**
@@ -201,10 +202,13 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
dma_addr_t curr_sgl_dma = 0;
struct acc_hw_sge *curr_hw_sge;
struct scatterlist *sg;
- int sg_n = sg_nents(sgl);
- int i, ret;
+ int i, ret, sg_n;
- if (!dev || !sgl || !pool || !hw_sgl_dma || sg_n > pool->sge_nr)
+ if (!dev || !sgl || !pool || !hw_sgl_dma)
+ return ERR_PTR(-EINVAL);
+
+ sg_n = sg_nents(sgl);
+ if (sg_n > pool->sge_nr)
return ERR_PTR(-EINVAL);
ret = dma_map_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
@@ -212,11 +216,12 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
return ERR_PTR(-EINVAL);
curr_hw_sgl = acc_get_sgl(pool, index, &curr_sgl_dma);
- if (!curr_hw_sgl) {
- ret = -ENOMEM;
- goto err_unmap_sg;
+ if (IS_ERR(curr_hw_sgl)) {
+ dma_unmap_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
+ return ERR_PTR(-ENOMEM);
+
}
- curr_hw_sgl->entry_length_in_sgl = pool->sge_nr;
+ curr_hw_sgl->entry_length_in_sgl = cpu_to_le16(pool->sge_nr);
curr_hw_sge = curr_hw_sgl->sge_entries;
for_each_sg(sgl, sg, sg_n, i) {
@@ -229,10 +234,6 @@ hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
*hw_sgl_dma = curr_sgl_dma;
return curr_hw_sgl;
-
-err_unmap_sg:
- dma_unmap_sg(dev, sgl, sg_n, DMA_BIDIRECTIONAL);
- return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_map_to_hw_sgl);
@@ -249,6 +250,9 @@ EXPORT_SYMBOL_GPL(hisi_acc_sg_buf_map_to_hw_sgl);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
struct hisi_acc_hw_sgl *hw_sgl)
{
+ if (!dev || !sgl || !hw_sgl)
+ return;
+
dma_unmap_sg(dev, sgl, sg_nents(sgl), DMA_BIDIRECTIONAL);
hw_sgl->entry_sum_in_chain = 0;
--
2.8.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 0/4] crypto: hisilicon: misc sgl fixes
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
` (3 preceding siblings ...)
2019-09-30 7:08 ` [PATCH 4/4] crypto: hisilicon - misc fix about sgl Zhou Wang
@ 2019-10-10 8:21 ` Zhou Wang
2019-10-10 12:54 ` Herbert Xu
5 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-10-10 8:21 UTC (permalink / raw)
To: Herbert Xu, David S. Miller; +Cc: linux-crypto, linuxarm
On 2019/9/30 15:08, Zhou Wang wrote:
> This series fixes some preblems in sgl code. The main change is merging sgl
> code into hisi_qm module.
>
> These problem are also fixed:
> - Let user driver to pass the configure of sge number in one sgl when
> creating hardware sgl resources.
> - When disabling SMMU, it may fail to allocate large continuous memory. We
> fixes this by allocating memory by blocks.
>
> This series is based on Arnd's patch: https://lkml.org/lkml/2019/9/19/455
Any comments for this series?
Best,
Zhou
>
> Shunkun Tan (1):
> crypto: hisilicon - add sgl_sge_nr module param for zip
>
> Zhou Wang (3):
> crypto: hisilicon - merge sgl support to hisi_qm module
> crypto: hisilicon - fix large sgl memory allocation problem when
> disable smmu
> crypto: hisilicon - misc fix about sgl
>
> MAINTAINERS | 1 -
> drivers/crypto/hisilicon/Kconfig | 9 --
> drivers/crypto/hisilicon/Makefile | 4 +-
> drivers/crypto/hisilicon/qm.h | 13 +++
> drivers/crypto/hisilicon/sgl.c | 182 +++++++++++++++++++-----------
> drivers/crypto/hisilicon/sgl.h | 24 ----
> drivers/crypto/hisilicon/zip/zip.h | 1 -
> drivers/crypto/hisilicon/zip/zip_crypto.c | 44 ++++++--
> 8 files changed, 167 insertions(+), 111 deletions(-)
> delete mode 100644 drivers/crypto/hisilicon/sgl.h
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/4] crypto: hisilicon: misc sgl fixes
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
` (4 preceding siblings ...)
2019-10-10 8:21 ` [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
@ 2019-10-10 12:54 ` Herbert Xu
2019-10-11 2:15 ` Zhou Wang
5 siblings, 1 reply; 8+ messages in thread
From: Herbert Xu @ 2019-10-10 12:54 UTC (permalink / raw)
To: Zhou Wang; +Cc: David S. Miller, linux-crypto, linuxarm
On Mon, Sep 30, 2019 at 03:08:51PM +0800, Zhou Wang wrote:
> This series fixes some preblems in sgl code. The main change is merging sgl
> code into hisi_qm module.
>
> These problem are also fixed:
> - Let user driver to pass the configure of sge number in one sgl when
> creating hardware sgl resources.
> - When disabling SMMU, it may fail to allocate large continuous memory. We
> fixes this by allocating memory by blocks.
>
> This series is based on Arnd's patch: https://lkml.org/lkml/2019/9/19/455
>
> Shunkun Tan (1):
> crypto: hisilicon - add sgl_sge_nr module param for zip
>
> Zhou Wang (3):
> crypto: hisilicon - merge sgl support to hisi_qm module
> crypto: hisilicon - fix large sgl memory allocation problem when
> disable smmu
> crypto: hisilicon - misc fix about sgl
>
> MAINTAINERS | 1 -
> drivers/crypto/hisilicon/Kconfig | 9 --
> drivers/crypto/hisilicon/Makefile | 4 +-
> drivers/crypto/hisilicon/qm.h | 13 +++
> drivers/crypto/hisilicon/sgl.c | 182 +++++++++++++++++++-----------
> drivers/crypto/hisilicon/sgl.h | 24 ----
> drivers/crypto/hisilicon/zip/zip.h | 1 -
> drivers/crypto/hisilicon/zip/zip_crypto.c | 44 ++++++--
> 8 files changed, 167 insertions(+), 111 deletions(-)
> delete mode 100644 drivers/crypto/hisilicon/sgl.h
All applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/4] crypto: hisilicon: misc sgl fixes
2019-10-10 12:54 ` Herbert Xu
@ 2019-10-11 2:15 ` Zhou Wang
0 siblings, 0 replies; 8+ messages in thread
From: Zhou Wang @ 2019-10-11 2:15 UTC (permalink / raw)
To: Herbert Xu; +Cc: David S. Miller, linux-crypto, linuxarm
On 2019/10/10 20:54, Herbert Xu wrote:
> On Mon, Sep 30, 2019 at 03:08:51PM +0800, Zhou Wang wrote:
>> This series fixes some preblems in sgl code. The main change is merging sgl
>> code into hisi_qm module.
>>
>> These problem are also fixed:
>> - Let user driver to pass the configure of sge number in one sgl when
>> creating hardware sgl resources.
>> - When disabling SMMU, it may fail to allocate large continuous memory. We
>> fixes this by allocating memory by blocks.
>>
>> This series is based on Arnd's patch: https://lkml.org/lkml/2019/9/19/455
>>
>> Shunkun Tan (1):
>> crypto: hisilicon - add sgl_sge_nr module param for zip
>>
>> Zhou Wang (3):
>> crypto: hisilicon - merge sgl support to hisi_qm module
>> crypto: hisilicon - fix large sgl memory allocation problem when
>> disable smmu
>> crypto: hisilicon - misc fix about sgl
>>
>> MAINTAINERS | 1 -
>> drivers/crypto/hisilicon/Kconfig | 9 --
>> drivers/crypto/hisilicon/Makefile | 4 +-
>> drivers/crypto/hisilicon/qm.h | 13 +++
>> drivers/crypto/hisilicon/sgl.c | 182 +++++++++++++++++++-----------
>> drivers/crypto/hisilicon/sgl.h | 24 ----
>> drivers/crypto/hisilicon/zip/zip.h | 1 -
>> drivers/crypto/hisilicon/zip/zip_crypto.c | 44 ++++++--
>> 8 files changed, 167 insertions(+), 111 deletions(-)
>> delete mode 100644 drivers/crypto/hisilicon/sgl.h
>
> All applied. Thanks.
Thanks.
Best,
Zhou
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-10-11 2:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-30 7:08 [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
2019-09-30 7:08 ` [PATCH 1/4] crypto: hisilicon - merge sgl support to hisi_qm module Zhou Wang
2019-09-30 7:08 ` [PATCH 2/4] crypto: hisilicon - add sgl_sge_nr module param for zip Zhou Wang
2019-09-30 7:08 ` [PATCH 3/4] crypto: hisilicon - fix large sgl memory allocation problem when disable smmu Zhou Wang
2019-09-30 7:08 ` [PATCH 4/4] crypto: hisilicon - misc fix about sgl Zhou Wang
2019-10-10 8:21 ` [PATCH 0/4] crypto: hisilicon: misc sgl fixes Zhou Wang
2019-10-10 12:54 ` Herbert Xu
2019-10-11 2:15 ` Zhou Wang
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