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From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, alison.schofield@intel.com,
	rafael@kernel.org, lukas@wunner.de
Subject: [PATCH v2 08/21] cxl: Add support for _DSM Function for retrieving QTG ID
Date: Mon, 27 Mar 2023 14:44:52 -0700	[thread overview]
Message-ID: <167995349254.2857312.13398539042888653099.stgit@djiang5-mobl3> (raw)
In-Reply-To: <167995336797.2857312.539473939839316778.stgit@djiang5-mobl3>

CXL spec v3.0 9.17.3 CXL Root Device Specific Methods (_DSM)

Add support to retrieve QTG ID via ACPI _DSM call. The _DSM call requires
an input of an ACPI package with 4 dwords (read latency, write latency,
read bandwidth, write bandwidth). The call returns a package with 1 WORD
that provides the max supported QTG ID and a package that may contain 0 or
more WORDs as the recommended QTG IDs in the recommended order.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>

---
v2:
- Reorder var declaration and use C99 style. (Jonathan)
- Allow >2 ACPI objects in package for future expansion. (Jonathan)
- Check QTG IDs against MAX QTG ID provided by output package. (Jonathan)
---
 drivers/cxl/core/Makefile |    1 
 drivers/cxl/core/acpi.c   |  116 +++++++++++++++++++++++++++++++++++++++++++++
 drivers/cxl/cxl.h         |   16 ++++++
 3 files changed, 133 insertions(+)
 create mode 100644 drivers/cxl/core/acpi.c

diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
index 867a8014b462..30d61c8cae22 100644
--- a/drivers/cxl/core/Makefile
+++ b/drivers/cxl/core/Makefile
@@ -13,5 +13,6 @@ cxl_core-y += mbox.o
 cxl_core-y += pci.o
 cxl_core-y += hdm.o
 cxl_core-y += cdat.o
+cxl_core-y += acpi.o
 cxl_core-$(CONFIG_TRACING) += trace.o
 cxl_core-$(CONFIG_CXL_REGION) += region.o
diff --git a/drivers/cxl/core/acpi.c b/drivers/cxl/core/acpi.c
new file mode 100644
index 000000000000..6eda5cad8d59
--- /dev/null
+++ b/drivers/cxl/core/acpi.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/acpi.h>
+#include <linux/pci.h>
+#include <asm/div64.h>
+#include "cxlpci.h"
+#include "cxl.h"
+
+const guid_t acpi_cxl_qtg_id_guid =
+	GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071,
+		  0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52);
+
+/**
+ * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
+ * @handle: ACPI handle
+ * @input: bandwidth and latency data
+ *
+ * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
+ * the QTG IDs that falls within the performance data.
+ */
+struct qtg_dsm_output *cxl_acpi_evaluate_qtg_dsm(acpi_handle handle,
+						 struct qtg_dsm_input *input)
+{
+	union acpi_object *out_obj, *out_buf, *pkg;
+	union acpi_object in_buf = {
+		.buffer = {
+			.type = ACPI_TYPE_BUFFER,
+			.pointer = (u8 *)input,
+			.length = sizeof(u32) * 4,
+		},
+	};
+	union acpi_object in_obj = {
+		.package = {
+			.type = ACPI_TYPE_PACKAGE,
+			.count = 1,
+			.elements = &in_buf
+		},
+	};
+	struct qtg_dsm_output *output = NULL;
+	int len, rc, i;
+	u16 *max_qtg;
+
+	out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
+	if (!out_obj)
+		return ERR_PTR(-ENXIO);
+
+	if (out_obj->type != ACPI_TYPE_PACKAGE) {
+		rc = -ENXIO;
+		goto err;
+	}
+
+	/* Check Max QTG ID */
+	pkg = &out_obj->package.elements[0];
+	if (pkg->type != ACPI_TYPE_BUFFER) {
+		rc = -ENXIO;
+		goto err;
+	}
+
+	if (pkg->buffer.length != sizeof(u16)) {
+		rc = -ENXIO;
+		goto err;
+	}
+	max_qtg = (u16 *)pkg->buffer.pointer;
+
+	/* Retrieve QTG IDs package */
+	pkg = &out_obj->package.elements[1];
+	if (pkg->type != ACPI_TYPE_PACKAGE) {
+		rc = -ENXIO;
+		goto err;
+	}
+
+	out_buf = &pkg->package.elements[0];
+	if (out_buf->type != ACPI_TYPE_BUFFER) {
+		rc = -ENXIO;
+		goto err;
+	}
+
+	len = out_buf->buffer.length;
+
+	/* It's legal to have 0 QTG entries */
+	if (len == 0)
+		goto out;
+
+	/* Malformed package, not multiple of WORD size */
+	if (len % sizeof(u16)) {
+		rc = -ENXIO;
+		goto out;
+	}
+
+	output = kmalloc(len + sizeof(*output), GFP_KERNEL);
+	if (!output) {
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	output->nr = len / sizeof(u16);
+	memcpy(output->qtg_ids, out_buf->buffer.pointer, len);
+
+	for (i = 0; i < output->nr; i++) {
+		if (output->qtg_ids[i] > *max_qtg)
+			pr_warn("QTG ID %u greater than MAX %u\n",
+				output->qtg_ids[i], *max_qtg);
+	}
+
+out:
+	ACPI_FREE(out_obj);
+	return output;
+
+err:
+	ACPI_FREE(out_obj);
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_acpi_evaluate_qtg_dsm, CXL);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 50ac74f66cbd..04b8a032bd14 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -7,6 +7,7 @@
 #include <linux/libnvdimm.h>
 #include <linux/bitfield.h>
 #include <linux/bitops.h>
+#include <linux/acpi.h>
 #include <linux/log2.h>
 #include <linux/list.h>
 #include <linux/io.h>
@@ -791,6 +792,21 @@ static inline struct cxl_dax_region *to_cxl_dax_region(struct device *dev)
 }
 #endif
 
+struct qtg_dsm_input {
+	u32 rd_lat;
+	u32 wr_lat;
+	u32 rd_bw;
+	u32 wr_bw;
+};
+
+struct qtg_dsm_output {
+	int nr;
+	u16 qtg_ids[];
+};
+
+struct qtg_dsm_output *cxl_acpi_evaluate_qtg_dsm(acpi_handle handle,
+						 struct qtg_dsm_input *input);
+
 /*
  * Unit test builds overrides this to __weak, find the 'strong' version
  * of these symbols in tools/testing/cxl/.



  parent reply	other threads:[~2023-03-27 21:44 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-27 21:44 [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-03-27 21:44 ` [PATCH v2 01/21] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-03-29 23:57   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 02/21] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-03-29  0:03   ` Alison Schofield
2023-03-29  0:21     ` Dave Jiang
2023-03-30  0:09   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 03/21] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-03-30  0:19   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 04/21] cxl: Add common helpers for cdat parsing Dave Jiang
2023-03-27 21:44 ` [PATCH v2 05/21] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-03-29  0:20   ` Alison Schofield
2023-03-29 20:41     ` Dave Jiang
2023-03-30 15:43   ` Dave Jiang
2023-03-27 21:44 ` [PATCH v2 06/21] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-03-29  0:44   ` Alison Schofield
2023-03-29 20:59     ` Dave Jiang
2023-03-29 21:59       ` Alison Schofield
2023-03-27 21:44 ` [PATCH v2 07/21] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-03-27 21:44 ` Dave Jiang [this message]
2023-03-27 21:44 ` [PATCH v2 09/21] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 10/21] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 11/21] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-03-27 21:45 ` [PATCH v2 12/21] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 13/21] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-03-27 21:45 ` [PATCH v2 14/21] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-03-27 21:45 ` [PATCH v2 15/21] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-03-27 21:45 ` [PATCH v2 16/21] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 17/21] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-03-27 21:45 ` [PATCH v2 18/21] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-03-27 21:46 ` [PATCH v2 19/21] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-03-27 21:46 ` [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-03-29  1:27   ` Alison Schofield
2023-03-29 21:44     ` Dave Jiang
2023-03-29 21:55   ` Dan Williams
2023-03-29 22:02     ` Dave Jiang
2023-03-27 21:46 ` [PATCH v2 21/21] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-03-29  1:13   ` Alison Schofield
2023-03-29 21:49     ` Dave Jiang
2023-03-28 17:45 ` [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang

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