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From: Dave Jiang <dave.jiang@intel.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, rafael@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 02/21] cxl: Add checksum verification to CDAT from CXL
Date: Tue, 28 Mar 2023 17:21:09 -0700	[thread overview]
Message-ID: <b28baa29-ed88-dcb2-68c6-df6cc8954795@intel.com> (raw)
In-Reply-To: <ZCOANlmHyhJ0hDGn@aschofie-mobl2>



On 3/28/23 5:03 PM, Alison Schofield wrote:
> On Mon, Mar 27, 2023 at 02:44:13PM -0700, Dave Jiang wrote:
>> A CDAT table is available from a CXL device. The table is read by the
>> driver and cached in software. With the CXL subsystem needing to parse the
>> CDAT table, the checksum should be verified. Add checksum verification
>> after the CDAT table is read from device.
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>>
>> ---
>> v2:
>> - Drop ACPI checksum export and just use local verification. (Dan)
>> ---
>>   drivers/cxl/core/pci.c |   16 ++++++++++++++++
>>   1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 25b7e8125d5d..e0d5e6525c0d 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -528,6 +528,16 @@ static int cxl_cdat_read_table(struct device *dev,
>>   	return 0;
>>   }
>>   
>> +static unsigned char cdat_checksum(void *buf, size_t size)
>> +{
>> +	unsigned char sum, *data = buf;
>> +	size_t i;
>> +
>> +	for (sum = 0, i = 0; i < size; i++)
>> +		sum += data[i];
>> +	return 0 - sum;
> 
> This return value isn't obvious to me. What's happening here?
> Thanks for explaining,

The expectation is that all the bytes add up to be equal 0 for the 
checksum verification. So if we get anything other than 0, the check 
would fail.

DJ

> 
> Alison
> 
>> +}
>> +
>>   /**
>>    * read_cdat_data - Read the CDAT data on this port
>>    * @port: Port to read data from
>> @@ -573,6 +583,12 @@ void read_cdat_data(struct cxl_port *port)
>>   	}
>>   
>>   	port->cdat.table = cdat_table + sizeof(__le32);
>> +	if (cdat_checksum(port->cdat.table, cdat_length)) {
>> +		/* Don't leave table data allocated on error */
>> +		devm_kfree(dev, cdat_table);
>> +		dev_err(dev, "CDAT data checksum error\n");
>> +	}
>> +
>>   	port->cdat.length = cdat_length;
>>   }
>>   EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
>>
>>

  reply	other threads:[~2023-03-29  0:21 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-27 21:44 [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-03-27 21:44 ` [PATCH v2 01/21] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-03-29 23:57   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 02/21] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-03-29  0:03   ` Alison Schofield
2023-03-29  0:21     ` Dave Jiang [this message]
2023-03-30  0:09   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 03/21] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-03-30  0:19   ` Ira Weiny
2023-03-27 21:44 ` [PATCH v2 04/21] cxl: Add common helpers for cdat parsing Dave Jiang
2023-03-27 21:44 ` [PATCH v2 05/21] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-03-29  0:20   ` Alison Schofield
2023-03-29 20:41     ` Dave Jiang
2023-03-30 15:43   ` Dave Jiang
2023-03-27 21:44 ` [PATCH v2 06/21] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-03-29  0:44   ` Alison Schofield
2023-03-29 20:59     ` Dave Jiang
2023-03-29 21:59       ` Alison Schofield
2023-03-27 21:44 ` [PATCH v2 07/21] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-03-27 21:44 ` [PATCH v2 08/21] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-03-27 21:44 ` [PATCH v2 09/21] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 10/21] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-03-27 21:45 ` [PATCH v2 11/21] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-03-27 21:45 ` [PATCH v2 12/21] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 13/21] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-03-27 21:45 ` [PATCH v2 14/21] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-03-27 21:45 ` [PATCH v2 15/21] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-03-27 21:45 ` [PATCH v2 16/21] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-03-27 21:45 ` [PATCH v2 17/21] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-03-27 21:45 ` [PATCH v2 18/21] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-03-27 21:46 ` [PATCH v2 19/21] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-03-27 21:46 ` [PATCH v2 20/21] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-03-29  1:27   ` Alison Schofield
2023-03-29 21:44     ` Dave Jiang
2023-03-29 21:55   ` Dan Williams
2023-03-29 22:02     ` Dave Jiang
2023-03-27 21:46 ` [PATCH v2 21/21] cxl/mem: Add debugfs output for QTG related data Dave Jiang
2023-03-29  1:13   ` Alison Schofield
2023-03-29 21:49     ` Dave Jiang
2023-03-28 17:45 ` [PATCH v2 00/21] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang

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