* [PATCH v3 3/5] arm64: dts: meson-axg: Add PCIE PHY node
[not found] <20191224173942.18160-1-repk@triplefau.lt>
@ 2019-12-24 17:39 ` Remi Pommarel
2019-12-24 17:39 ` [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2 siblings, 0 replies; 7+ messages in thread
From: Remi Pommarel @ 2019-12-24 17:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl
Cc: Jerome Brunet, linux-amlogic, linux-pci, linux-kernel,
Remi Pommarel, devicetree
Enable PCIE PHY node to make PCIE reliable on AXG SoC.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 04803c3bccfa..e679ef26ab79 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -1356,6 +1356,15 @@ tdmout_c: audio-controller@580 {
};
};
+ pcie_phy: pcie-phy@ff644000 {
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x2000>;
+ aml,hhi-gpr = <&sysctrl>;
+ resets = <&reset RESET_PCIE_PHY>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
--
2.24.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation
[not found] <20191224173942.18160-1-repk@triplefau.lt>
2019-12-24 17:39 ` [PATCH v3 3/5] arm64: dts: meson-axg: Add PCIE PHY node Remi Pommarel
@ 2019-12-24 17:39 ` Remi Pommarel
2020-01-04 0:21 ` Rob Herring
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2 siblings, 1 reply; 7+ messages in thread
From: Remi Pommarel @ 2019-12-24 17:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl
Cc: Jerome Brunet, linux-amlogic, linux-pci, linux-kernel,
Remi Pommarel, devicetree
Now that a new PHYs has been introduced for AXG SoC family, update
dt bindings documentation.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
.../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++-----------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
index 84fdc422792e..b6acbe694ffb 100644
--- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -18,7 +18,6 @@ Required properties:
- reg-names: Must be
- "elbi" External local bus interface registers
- "cfg" Meson specific registers
- - "phy" Meson PCIE PHY registers for AXG SoC Family
- "config" PCIe configuration space
- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
- clocks: Must contain an entry for each entry in clock-names.
@@ -26,13 +25,13 @@ Required properties:
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A or B) RC clock gate
- "general" PCIe Phy clock
- - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
- resets: phandle to the reset lines.
-- reset-names: must contain "phy" "port" and "apb"
- - "phy" Share PHY reset for AXG SoC Family
+- reset-names: must contain "port" and "apb"
- "port" Port A or B reset
- "apb" Share APB reset
-- phys: should contain a phandle to the shared phy for G12A SoC Family
+- phys: should contain a phandle to the PCIE phy
+- phy-names: must contain "pcie"
+
- device_type:
should be "pci". As specified in designware-pcie.txt
@@ -43,9 +42,8 @@ Example configuration:
compatible = "amlogic,axg-pcie", "snps,dw-pcie";
reg = <0x0 0xf9800000 0x0 0x400000
0x0 0xff646000 0x0 0x2000
- 0x0 0xff644000 0x0 0x2000
0x0 0xf9f00000 0x0 0x100000>;
- reg-names = "elbi", "cfg", "phy", "config";
+ reg-names = "elbi", "cfg", "config";
reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
@@ -58,17 +56,15 @@ Example configuration:
ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
clocks = <&clkc CLKID_USB
- &clkc CLKID_MIPI_ENABLE
&clkc CLKID_PCIE_A
&clkc CLKID_PCIE_CML_EN0>;
clock-names = "general",
- "mipi",
"pclk",
"port";
- resets = <&reset RESET_PCIE_PHY>,
- <&reset RESET_PCIE_A>,
+ resets = <&reset RESET_PCIE_A>,
<&reset RESET_PCIE_APB>;
- reset-names = "phy",
- "port",
+ reset-names = "port",
"apb";
+ phys = <&pcie_phy>;
+ phy-names = "pcie";
};
--
2.24.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings
[not found] <20191224173942.18160-1-repk@triplefau.lt>
2019-12-24 17:39 ` [PATCH v3 3/5] arm64: dts: meson-axg: Add PCIE PHY node Remi Pommarel
2019-12-24 17:39 ` [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
@ 2019-12-24 17:39 ` Remi Pommarel
2019-12-25 19:02 ` Remi Pommarel
` (2 more replies)
2 siblings, 3 replies; 7+ messages in thread
From: Remi Pommarel @ 2019-12-24 17:39 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl
Cc: Jerome Brunet, linux-amlogic, linux-pci, linux-kernel,
Remi Pommarel, devicetree
Add documentation for PCIE PHYs found in AXG SoCs.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
---
.../bindings/phy/amlogic,meson-axg-pcie.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
new file mode 100644
index 000000000000..c622a1b38ffc
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic AXG PCIE PHY
+
+maintainers:
+ - Remi Pommarel <repk@triplefau.lt>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,axg-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ aml,hhi-gpr:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: phy
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - aml,hhi-gpr
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+examples:
+ - |
+ pcie_phy: pcie-phy@ff644000 {
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x2000>;
+ aml,hhi-gpr = <&sysctrl>;
+ resets = <&reset RESET_PCIE_PHY>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
--
2.24.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
@ 2019-12-25 19:02 ` Remi Pommarel
2019-12-26 20:10 ` Martin Blumenstingl
2020-01-04 0:24 ` Rob Herring
2 siblings, 0 replies; 7+ messages in thread
From: Remi Pommarel @ 2019-12-25 19:02 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl
Cc: Jerome Brunet, linux-amlogic, linux-pci, linux-kernel, devicetree
On Tue, Dec 24, 2019 at 06:39:42PM +0100, Remi Pommarel wrote:
> Add documentation for PCIE PHYs found in AXG SoCs.
>
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> ---
> .../bindings/phy/amlogic,meson-axg-pcie.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> new file mode 100644
> index 000000000000..c622a1b38ffc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic AXG PCIE PHY
> +
> +maintainers:
> + - Remi Pommarel <repk@triplefau.lt>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,axg-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + aml,hhi-gpr:
> + maxItems: 1
My bad, I didn't know about devicetree schemas and their verification,
I will fix the missing $ref: '/schemas/types.yaml#/definitions/phandle'
here, add a description and add the missing include for reset in the
example below in v4 along with upcoming comments on the other patches.
Sorry about that.
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: phy
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - aml,hhi-gpr
> + - resets
> + - reset-names
> + - "#phy-cells"
> +
> +examples:
> + - |
> + pcie_phy: pcie-phy@ff644000 {
> + compatible = "amlogic,axg-pcie-phy";
> + reg = <0x0 0xff644000 0x0 0x2000>;
> + aml,hhi-gpr = <&sysctrl>;
> + resets = <&reset RESET_PCIE_PHY>;
> + reset-names = "phy";
> + #phy-cells = <0>;
> + };
> --
> 2.24.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2019-12-25 19:02 ` Remi Pommarel
@ 2019-12-26 20:10 ` Martin Blumenstingl
2020-01-04 0:24 ` Rob Herring
2 siblings, 0 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2019-12-26 20:10 UTC (permalink / raw)
To: Remi Pommarel
Cc: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Jerome Brunet,
linux-amlogic, linux-pci, linux-kernel, devicetree
On Tue, Dec 24, 2019 at 6:32 PM Remi Pommarel <repk@triplefau.lt> wrote:
>
> Add documentation for PCIE PHYs found in AXG SoCs.
>
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> ---
> .../bindings/phy/amlogic,meson-axg-pcie.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> new file mode 100644
> index 000000000000..c622a1b38ffc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic AXG PCIE PHY
> +
> +maintainers:
> + - Remi Pommarel <repk@triplefau.lt>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,axg-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + aml,hhi-gpr:
> + maxItems: 1
nit-pick (as I didn't have time to review the whole series yet):
we have at least two other IP blocks that need this. they use
"amlogic,hhi-sysctrl" for the property name
Martin
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation
2019-12-24 17:39 ` [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
@ 2020-01-04 0:21 ` Rob Herring
0 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2020-01-04 0:21 UTC (permalink / raw)
To: Remi Pommarel
Cc: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Jerome Brunet, linux-amlogic, linux-pci, linux-kernel,
devicetree
On Tue, Dec 24, 2019 at 06:39:41PM +0100, Remi Pommarel wrote:
> Now that a new PHYs has been introduced for AXG SoC family, update
> dt bindings documentation.
This breaks compatibility. If that's okay, say so and why it is.
If only someone had said putting the phy here in the first place was
wrong:
https://lore.kernel.org/linux-amlogic/20180829004122.GA25928@bogus/
>
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> ---
> .../bindings/pci/amlogic,meson-pcie.txt | 22 ++++++++-----------
> 1 file changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> index 84fdc422792e..b6acbe694ffb 100644
> --- a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> @@ -18,7 +18,6 @@ Required properties:
> - reg-names: Must be
> - "elbi" External local bus interface registers
> - "cfg" Meson specific registers
> - - "phy" Meson PCIE PHY registers for AXG SoC Family
> - "config" PCIe configuration space
> - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
> - clocks: Must contain an entry for each entry in clock-names.
> @@ -26,13 +25,13 @@ Required properties:
> - "pclk" PCIe GEN 100M PLL clock
> - "port" PCIe_x(A or B) RC clock gate
> - "general" PCIe Phy clock
> - - "mipi" PCIe_x(A or B) 100M ref clock gate for AXG SoC Family
> - resets: phandle to the reset lines.
> -- reset-names: must contain "phy" "port" and "apb"
> - - "phy" Share PHY reset for AXG SoC Family
> +- reset-names: must contain "port" and "apb"
> - "port" Port A or B reset
> - "apb" Share APB reset
> -- phys: should contain a phandle to the shared phy for G12A SoC Family
> +- phys: should contain a phandle to the PCIE phy
> +- phy-names: must contain "pcie"
> +
> - device_type:
> should be "pci". As specified in designware-pcie.txt
>
> @@ -43,9 +42,8 @@ Example configuration:
> compatible = "amlogic,axg-pcie", "snps,dw-pcie";
> reg = <0x0 0xf9800000 0x0 0x400000
> 0x0 0xff646000 0x0 0x2000
> - 0x0 0xff644000 0x0 0x2000
> 0x0 0xf9f00000 0x0 0x100000>;
> - reg-names = "elbi", "cfg", "phy", "config";
> + reg-names = "elbi", "cfg", "config";
> reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
> interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
> #interrupt-cells = <1>;
> @@ -58,17 +56,15 @@ Example configuration:
> ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
>
> clocks = <&clkc CLKID_USB
> - &clkc CLKID_MIPI_ENABLE
> &clkc CLKID_PCIE_A
> &clkc CLKID_PCIE_CML_EN0>;
> clock-names = "general",
> - "mipi",
> "pclk",
> "port";
> - resets = <&reset RESET_PCIE_PHY>,
> - <&reset RESET_PCIE_A>,
> + resets = <&reset RESET_PCIE_A>,
> <&reset RESET_PCIE_APB>;
> - reset-names = "phy",
> - "port",
> + reset-names = "port",
> "apb";
> + phys = <&pcie_phy>;
> + phy-names = "pcie";
> };
> --
> 2.24.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2019-12-25 19:02 ` Remi Pommarel
2019-12-26 20:10 ` Martin Blumenstingl
@ 2020-01-04 0:24 ` Rob Herring
2 siblings, 0 replies; 7+ messages in thread
From: Rob Herring @ 2020-01-04 0:24 UTC (permalink / raw)
To: Remi Pommarel
Cc: Kishon Vijay Abraham I, Yue Wang, Lorenzo Pieralisi,
Andrew Murray, Neil Armstrong, Kevin Hilman, Martin Blumenstingl,
Jerome Brunet, linux-amlogic, linux-pci, linux-kernel,
devicetree
On Tue, Dec 24, 2019 at 06:39:42PM +0100, Remi Pommarel wrote:
> Add documentation for PCIE PHYs found in AXG SoCs.
>
> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
> ---
> .../bindings/phy/amlogic,meson-axg-pcie.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> new file mode 100644
> index 000000000000..c622a1b38ffc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-axg-pcie.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-pcie.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic AXG PCIE PHY
> +
> +maintainers:
> + - Remi Pommarel <repk@triplefau.lt>
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,axg-pcie-phy
Do you expect another compatible? If not, use 'const' instead.
> +
> + reg:
> + maxItems: 1
> +
> + aml,hhi-gpr:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: phy
You don't need *-names when there's only one entry.
> +
> + "#phy-cells":
> + const: 0
> +
> +required:
> + - compatible
> + - reg
> + - aml,hhi-gpr
> + - resets
> + - reset-names
> + - "#phy-cells"
> +
> +examples:
> + - |
> + pcie_phy: pcie-phy@ff644000 {
> + compatible = "amlogic,axg-pcie-phy";
> + reg = <0x0 0xff644000 0x0 0x2000>;
> + aml,hhi-gpr = <&sysctrl>;
> + resets = <&reset RESET_PCIE_PHY>;
> + reset-names = "phy";
> + #phy-cells = <0>;
> + };
> --
> 2.24.0
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-01-04 0:24 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20191224173942.18160-1-repk@triplefau.lt>
2019-12-24 17:39 ` [PATCH v3 3/5] arm64: dts: meson-axg: Add PCIE PHY node Remi Pommarel
2019-12-24 17:39 ` [PATCH v3 4/5] dt-bindings: PCI: meson: Update PCIE bindings documentation Remi Pommarel
2020-01-04 0:21 ` Rob Herring
2019-12-24 17:39 ` [PATCH v3 5/5] dt-bindings: Add AXG PCIE PHY bindings Remi Pommarel
2019-12-25 19:02 ` Remi Pommarel
2019-12-26 20:10 ` Martin Blumenstingl
2020-01-04 0:24 ` Rob Herring
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