From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>
Subject: [RFC PATCH v3 10/10] EDAC/amd64: Check for memory before fully initializing an instance
Date: Thu, 22 Aug 2019 00:00:03 +0000 [thread overview]
Message-ID: <20190821235938.118710-11-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20190821235938.118710-1-Yazen.Ghannam@amd.com>
From: Yazen Ghannam <yazen.ghannam@amd.com>
Return early before checking for ECC if the node does not have any
populated memory.
Free any cached hardware data before returning. Also, return 0 in this
case since this is not a failure. Other nodes may have memory and the
module should attempt to load an instance for them.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
drivers/edac/amd64_edac.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c1cb0234f085..7230ed4ff665 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3505,6 +3505,23 @@ static int init_one_instance(struct amd64_pvt *pvt,
return ret;
}
+static bool instance_has_memory(struct amd64_pvt *pvt)
+{
+ bool cs_enabled = false;
+ int num_channels = 2;
+ int cs = 0, dct = 0;
+
+ if (pvt->umc)
+ num_channels = num_umcs;
+
+ for (dct = 0; dct < num_channels; dct++) {
+ for_each_chip_select(cs, dct, pvt)
+ cs_enabled |= csrow_enabled(cs, dct, pvt);
+ }
+
+ return cs_enabled;
+}
+
static int probe_one_instance(unsigned int nid)
{
struct pci_dev *F3 = node_to_amd_nb(nid)->misc;
@@ -3535,6 +3552,10 @@ static int probe_one_instance(unsigned int nid)
if (ret < 0)
goto err_enable;
+ ret = 0;
+ if (!instance_has_memory(pvt))
+ goto err_enable;
+
if (!ecc_enabled(pvt)) {
ret = 0;
--
2.17.1
next prev parent reply other threads:[~2019-08-22 0:00 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 23:59 [PATCH v3 0/8] AMD64 EDAC fixes Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 1/8] EDAC/amd64: Support more than two controllers for chip selects handling Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 2/8] EDAC/amd64: Recognize DRAM device type with EDAC_CTL_CAP Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 3/8] EDAC/amd64: Initialize DIMM info for systems with more than two channels Ghannam, Yazen
2019-08-21 23:59 ` [PATCH v3 4/8] EDAC/amd64: Find Chip Select memory size using Address Mask Ghannam, Yazen
2019-08-22 0:00 ` [PATCH v3 5/8] EDAC/amd64: Decode syndrome before translating address Ghannam, Yazen
2019-08-22 0:00 ` [PATCH v3 6/8] EDAC/amd64: Cache secondary Chip Select registers Ghannam, Yazen
2019-08-22 0:00 ` [RFC PATCH v3 08/10] EDAC/amd64: Gather hardware information early Ghannam, Yazen
2019-08-29 9:22 ` Borislav Petkov
2019-09-06 19:14 ` Ghannam, Yazen
2019-09-06 20:35 ` Borislav Petkov
2019-09-06 20:49 ` Ghannam, Yazen
2019-09-09 15:31 ` Borislav Petkov
2019-08-22 0:00 ` [PATCH v3 7/8] EDAC/amd64: Support Asymmetric Dual-Rank DIMMs Ghannam, Yazen
2019-08-23 11:26 ` Borislav Petkov
2019-08-23 13:27 ` Ghannam, Yazen
2019-08-23 15:11 ` Borislav Petkov
2019-08-22 0:00 ` Ghannam, Yazen [this message]
2019-08-22 18:51 ` [RFC PATCH v2] EDAC/amd64: Check for memory before fully initializing an instance Ghannam, Yazen
2019-08-22 0:00 ` [RFC PATCH v3 09/10] EDAC/amd64: Use cached data when checking for ECC Ghannam, Yazen
2019-08-22 0:50 ` [PATCH v3 0/8] AMD64 EDAC fixes Adam Borowski
2019-08-22 8:35 ` Borislav Petkov
2019-08-22 9:46 ` Adam Borowski
2019-08-22 9:55 ` Borislav Petkov
2019-08-22 18:54 ` Ghannam, Yazen
2019-08-23 15:28 ` Ghannam, Yazen
2019-08-23 15:37 ` Borislav Petkov
2019-08-26 14:19 ` Ghannam, Yazen
2019-08-26 14:59 ` Borislav Petkov
2019-08-26 15:05 ` Ghannam, Yazen
2019-08-22 18:48 ` [RFC PATCH v2] EDAC/amd64: Check for memory before fully initializing an instance Ghannam, Yazen
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