[PATCH 0/2] Fix i10nm_edac driver load failure

From: Tony Luck <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Tony Luck <tony.luck@intel.com>,
	Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
	Aristeu Rozanski <aris@redhat.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	linux-edac@vger.kernel.org
Subject: [PATCH 0/2] Fix i10nm_edac driver load failure
Date: Fri, 24 Apr 2020 11:57:36 -0700	[thread overview]
Message-ID: <20200424185738.7985-1-tony.luck@intel.com> (raw)

The root cause is that one of the configuration registers
needed by EDAC changed offset between pre-production and
final stepping of some CPU models. Ordinarily we might fix
this by just making the driver only support the production
stepping. But there are still significant numbers of the
pre-production parts in use (both within Intel and with
customers), so we need to adapt to use the right offset
for the register depending on both model and stepping.

Patch 1: Adds a configuration structure to make this, and future
changes, possible.
Patch 2: Adjusts the register offset

Qiuxu Zhuo (2):
  EDAC, {skx,i10nm}: Make some configurations CPU model specific
  EDAC, i10nm: Fix i10nm_edac loading failure on some servers

 drivers/edac/i10nm_base.c | 28 ++++++++++++++++++++++++----
 drivers/edac/skx_base.c   | 12 ++++++++++--
 drivers/edac/skx_common.c | 11 +++++------
 drivers/edac/skx_common.h | 11 +++++++++--
 4 files changed, 48 insertions(+), 14 deletions(-)

-- 
2.21.1