From: Tony Luck <tony.luck@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Jerry Chen <jerry.t.chen@intel.com>, Jin Wen <wen.jin@intel.com>,
Tony Luck <tony.luck@intel.com>,
Aristeu Rozanski <aris@redhat.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-edac@vger.kernel.org
Subject: [PATCH 2/2] EDAC, i10nm: Fix i10nm_edac loading failure on some servers
Date: Fri, 24 Apr 2020 11:57:38 -0700 [thread overview]
Message-ID: <20200424185738.7985-3-tony.luck@intel.com> (raw)
In-Reply-To: <20200424185738.7985-1-tony.luck@intel.com>
From: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
It failed to load the i10nm_edac driver on Ice Lake and
Tremont/Jacobsville servers if their CPU stepping >= 4 and failed
on Ice Lake-D servers from stepping 0. The root cause was that for
Ice Lake and Tremont/Jacobsville servers with CPU stepping >=4, the
offset for bus number configuration register was updated from 0xcc
to 0xd0. For Ice Lake-D servers, all the steppings use the updated
0xd0 offset.
Fix the issue by using the appropriate offset for bus number
configuration register according to the CPU model number and stepping.
Reported-by: Jerry Chen <jerry.t.chen@intel.com>
Reported-and-tested-by: Jin Wen <wen.jin@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
drivers/edac/i10nm_base.c | 20 ++++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/edac/i10nm_base.c b/drivers/edac/i10nm_base.c
index ba4578c6ef2b..ebb45738c11b 100644
--- a/drivers/edac/i10nm_base.c
+++ b/drivers/edac/i10nm_base.c
@@ -122,16 +122,24 @@ static int i10nm_get_all_munits(void)
return 0;
}
-static struct res_config i10nm_cfg = {
+/* ATOM_TREMONT_D, ICELAKE_X */
+static struct res_config i10nm_cfg0 = {
.type = I10NM,
.decs_did = 0x3452,
.busno_cfg_offset = 0xcc,
};
+/* ICELAKE_D */
+static struct res_config i10nm_cfg1 = {
+ .type = I10NM,
+ .decs_did = 0x3452,
+ .busno_cfg_offset = 0xd0,
+};
+
static const struct x86_cpu_id i10nm_cpuids[] = {
- X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg),
- X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg),
- X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg0),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg0),
+ X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg1),
{}
};
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
@@ -257,6 +265,10 @@ static int __init i10nm_init(void)
return -ENODEV;
cfg = (struct res_config *)id->driver_data;
+ /* Newer steppings have different offset for ATOM_TREMONT_D/ICELAKE_X */
+ if (boot_cpu_data.x86_stepping >= 4)
+ cfg->busno_cfg_offset = 0xd0;
+
rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
if (rc)
return rc;
--
2.21.1
next prev parent reply other threads:[~2020-04-24 18:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-24 18:57 [PATCH 0/2] Fix i10nm_edac driver load failure Tony Luck
2020-04-24 18:57 ` [PATCH 1/2] EDAC, {skx,i10nm}: Make some configurations CPU model specific Tony Luck
2020-04-27 8:32 ` Borislav Petkov
2020-04-24 18:57 ` Tony Luck [this message]
2020-04-27 8:40 ` [PATCH 2/2] EDAC, i10nm: Fix i10nm_edac loading failure on some servers Borislav Petkov
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