From: Luca Ceresoli <luca@lucaceresoli.net>
To: linux-fpga@vger.kernel.org
Cc: Luca Ceresoli <luca@lucaceresoli.net>,
Moritz Fischer <mdf@kernel.org>, Tom Rix <trix@redhat.com>,
Michal Simek <michal.simek@xilinx.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Anatolij Gustschin <agust@denx.de>
Subject: [PATCH v2 2/5] fpga manager: xilinx-spi: remove final dot from dev_err() strings
Date: Thu, 27 Aug 2020 16:32:46 +0200 [thread overview]
Message-ID: <20200827143249.10973-2-luca@lucaceresoli.net> (raw)
In-Reply-To: <20200827143249.10973-1-luca@lucaceresoli.net>
Most dev_err messages in this file have no final dot. Remove the only two
exceptions to make them consistent.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
---
Changes in v2:
- move before the "provide better diagnostics on programming failure"
patch for clarity
---
drivers/fpga/xilinx-spi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
index 502fae0d1d85..01f494172379 100644
--- a/drivers/fpga/xilinx-spi.c
+++ b/drivers/fpga/xilinx-spi.c
@@ -77,7 +77,7 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr,
int err;
if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
- dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
+ dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
return -EINVAL;
}
@@ -169,7 +169,7 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr,
return xilinx_spi_apply_cclk_cycles(conf);
}
- dev_err(&mgr->dev, "Timeout after config data transfer.\n");
+ dev_err(&mgr->dev, "Timeout after config data transfer\n");
return -ETIMEDOUT;
}
--
2.28.0
next prev parent reply other threads:[~2020-08-27 14:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-27 14:32 [PATCH v2 1/5] fpga manager: xilinx-spi: remove stray comment Luca Ceresoli
2020-08-27 14:32 ` Luca Ceresoli [this message]
2020-08-27 14:32 ` [PATCH v2 3/5] fpga manager: xilinx-spi: rework write_complete loop implementation Luca Ceresoli
2020-08-27 18:59 ` Tom Rix
2020-08-27 19:26 ` Luca Ceresoli
[not found] ` <27bbb896-fedf-6a3a-7220-5c57239a3b87@redhat.com>
2020-08-28 6:38 ` Luca Ceresoli
2020-08-28 12:34 ` Tom Rix
2020-08-27 14:32 ` [PATCH v2 4/5] fpga manager: xilinx-spi: add error checking after gpiod_get_value() Luca Ceresoli
2020-08-27 19:04 ` Tom Rix
2020-08-27 14:32 ` [PATCH v2 5/5] fpga manager: xilinx-spi: provide better diagnostics on programming failure Luca Ceresoli
2020-08-27 19:09 ` Tom Rix
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