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From: Luca Ceresoli <luca@lucaceresoli.net>
To: linux-fpga@vger.kernel.org
Cc: Luca Ceresoli <luca@lucaceresoli.net>,
	Moritz Fischer <mdf@kernel.org>, Tom Rix <trix@redhat.com>,
	Michal Simek <michal.simek@xilinx.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Anatolij Gustschin <agust@denx.de>
Subject: [PATCH v2 4/5] fpga manager: xilinx-spi: add error checking after gpiod_get_value()
Date: Thu, 27 Aug 2020 16:32:48 +0200	[thread overview]
Message-ID: <20200827143249.10973-4-luca@lucaceresoli.net> (raw)
In-Reply-To: <20200827143249.10973-1-luca@lucaceresoli.net>

Current code calls gpiod_get_value() without error checking. Should the
GPIO controller fail, execution would continue without any error message.

Fix by checking for negative error values.

Reported-by: Tom Rix <trix@redhat.com>
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>

---

This patch is new in v2
---
 drivers/fpga/xilinx-spi.c | 40 ++++++++++++++++++++++++++++++---------
 1 file changed, 31 insertions(+), 9 deletions(-)

diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
index cfc933d70f52..bcc740ec42f5 100644
--- a/drivers/fpga/xilinx-spi.c
+++ b/drivers/fpga/xilinx-spi.c
@@ -27,11 +27,22 @@ struct xilinx_spi_conf {
 	struct gpio_desc *done;
 };
 
-static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
+static int get_done_gpio(struct fpga_manager *mgr)
 {
 	struct xilinx_spi_conf *conf = mgr->priv;
+	int ret;
+
+	ret = gpiod_get_value(conf->done);
 
-	if (!gpiod_get_value(conf->done))
+	if (ret < 0)
+		dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
+
+	return ret;
+}
+
+static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
+{
+	if (!get_done_gpio(mgr))
 		return FPGA_MGR_STATE_RESET;
 
 	return FPGA_MGR_STATE_UNKNOWN;
@@ -57,10 +68,21 @@ static int wait_for_init_b(struct fpga_manager *mgr, int value,
 
 	if (conf->init_b) {
 		while (time_before(jiffies, timeout)) {
-			if (gpiod_get_value(conf->init_b) == value)
+			int ret = gpiod_get_value(conf->init_b);
+
+			if (ret == value)
 				return 0;
+
+			if (ret < 0) {
+				dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
+				return ret;
+			}
+
 			usleep_range(100, 400);
 		}
+
+		dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
+			value ? "assert" : "deassert");
 		return -ETIMEDOUT;
 	}
 
@@ -85,7 +107,6 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr,
 
 	err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
 	if (err) {
-		dev_err(&mgr->dev, "INIT_B pin did not go low\n");
 		gpiod_set_value(conf->prog_b, 0);
 		return err;
 	}
@@ -93,12 +114,10 @@ static int xilinx_spi_write_init(struct fpga_manager *mgr,
 	gpiod_set_value(conf->prog_b, 0);
 
 	err = wait_for_init_b(mgr, 0, 0);
-	if (err) {
-		dev_err(&mgr->dev, "INIT_B pin did not go high\n");
+	if (err)
 		return err;
-	}
 
-	if (gpiod_get_value(conf->done)) {
+	if (get_done_gpio(mgr)) {
 		dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
 		return -EIO;
 	}
@@ -155,7 +174,10 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr,
 	int ret;
 
 	while (true) {
-		if (gpiod_get_value(conf->done))
+		ret = get_done_gpio(mgr);
+		if (ret < 0)
+			return ret;
+		if (ret)
 			return xilinx_spi_apply_cclk_cycles(conf);
 
 		if (time_after(jiffies, timeout))
-- 
2.28.0


  parent reply	other threads:[~2020-08-27 14:33 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-27 14:32 [PATCH v2 1/5] fpga manager: xilinx-spi: remove stray comment Luca Ceresoli
2020-08-27 14:32 ` [PATCH v2 2/5] fpga manager: xilinx-spi: remove final dot from dev_err() strings Luca Ceresoli
2020-08-27 14:32 ` [PATCH v2 3/5] fpga manager: xilinx-spi: rework write_complete loop implementation Luca Ceresoli
2020-08-27 18:59   ` Tom Rix
2020-08-27 19:26     ` Luca Ceresoli
     [not found]       ` <27bbb896-fedf-6a3a-7220-5c57239a3b87@redhat.com>
2020-08-28  6:38         ` Luca Ceresoli
2020-08-28 12:34           ` Tom Rix
2020-08-27 14:32 ` Luca Ceresoli [this message]
2020-08-27 19:04   ` [PATCH v2 4/5] fpga manager: xilinx-spi: add error checking after gpiod_get_value() Tom Rix
2020-08-27 14:32 ` [PATCH v2 5/5] fpga manager: xilinx-spi: provide better diagnostics on programming failure Luca Ceresoli
2020-08-27 19:09   ` Tom Rix

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