* [PATCH] gpio: cadence: Pass irqchip when adding gpiochip
@ 2019-08-09 13:18 Linus Walleij
2019-08-12 9:53 ` Jan Kotas
0 siblings, 1 reply; 3+ messages in thread
From: Linus Walleij @ 2019-08-09 13:18 UTC (permalink / raw)
To: linux-gpio; +Cc: Bartosz Golaszewski, Linus Walleij, Jan Kotas, Thierry Reding
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.
For chained irqchips this is a pretty straight-forward
conversion.
Cc: Jan Kotas <jank@cadence.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Hi Jan, it'd be great if you could test/review this
patch.
---
drivers/gpio/gpio-cadence.c | 36 +++++++++++++++++++++---------------
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpio/gpio-cadence.c b/drivers/gpio/gpio-cadence.c
index 712ae212b0b4..a4d3239d2594 100644
--- a/drivers/gpio/gpio-cadence.c
+++ b/drivers/gpio/gpio-cadence.c
@@ -214,27 +214,33 @@ static int cdns_gpio_probe(struct platform_device *pdev)
goto err_revert_dir;
}
- ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
- if (ret < 0) {
- dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
- goto err_disable_clk;
- }
-
/*
- * irq_chip support
+ * Optional irq_chip support
*/
irq = platform_get_irq(pdev, 0);
if (irq >= 0) {
- ret = gpiochip_irqchip_add(&cgpio->gc, &cdns_gpio_irqchip,
- 0, handle_level_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&pdev->dev, "Could not add irqchip, %d\n",
- ret);
+ struct gpio_irq_chip *girq;
+
+ girq = &cgpio->gc.irq;
+ girq->chip = &cdns_gpio_irqchip;
+ girq->parent_handler = cdns_gpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(&pdev->dev, 1,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents) {
+ ret = -ENOMEM;
goto err_disable_clk;
}
- gpiochip_set_chained_irqchip(&cgpio->gc, &cdns_gpio_irqchip,
- irq, cdns_gpio_irq_handler);
+ girq->parents[0] = irq;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_level_irq;
+ }
+
+ ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
+ goto err_disable_clk;
}
cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
--
2.21.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] gpio: cadence: Pass irqchip when adding gpiochip
2019-08-09 13:18 [PATCH] gpio: cadence: Pass irqchip when adding gpiochip Linus Walleij
@ 2019-08-12 9:53 ` Jan Kotas
2019-08-14 8:37 ` Linus Walleij
0 siblings, 1 reply; 3+ messages in thread
From: Jan Kotas @ 2019-08-12 9:53 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski, Jan Kotas, Thierry Reding
> On 9 Aug 2019, at 15:18, Linus Walleij <linus.walleij@linaro.org> wrote:
>
> We need to convert all old gpio irqchips to pass the irqchip
> setup along when adding the gpio_chip. For more info see
> drivers/gpio/TODO.
>
> For chained irqchips this is a pretty straight-forward
> conversion.
>
> Cc: Jan Kotas <jank@cadence.com>
> Cc: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Hi Jan, it'd be great if you could test/review this
> patch.
Everything seems to be OK in my tests.
Regards,
Jan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] gpio: cadence: Pass irqchip when adding gpiochip
2019-08-12 9:53 ` Jan Kotas
@ 2019-08-14 8:37 ` Linus Walleij
0 siblings, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2019-08-14 8:37 UTC (permalink / raw)
To: Jan Kotas; +Cc: linux-gpio, Bartosz Golaszewski, Thierry Reding
On Mon, Aug 12, 2019 at 11:53 AM Jan Kotas <jank@cadence.com> wrote:
> > On 9 Aug 2019, at 15:18, Linus Walleij <linus.walleij@linaro.org> wrote:
> >
> > We need to convert all old gpio irqchips to pass the irqchip
> > setup along when adding the gpio_chip. For more info see
> > drivers/gpio/TODO.
> >
> > For chained irqchips this is a pretty straight-forward
> > conversion.
> >
> > Cc: Jan Kotas <jank@cadence.com>
> > Cc: Thierry Reding <treding@nvidia.com>
> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> > ---
> > Hi Jan, it'd be great if you could test/review this
> > patch.
>
> Everything seems to be OK in my tests.
Thanks, recorded as Tested-by and applied!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-08-09 13:18 [PATCH] gpio: cadence: Pass irqchip when adding gpiochip Linus Walleij
2019-08-12 9:53 ` Jan Kotas
2019-08-14 8:37 ` Linus Walleij
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