[RFC PATCH] [media] mt9v032: reset is self clearing

[RFC PATCH] [media] mt9v032: reset is self clearing

[Philipp Zabel]

According to the publicly available MT9V032 data sheet, the reset bits are self
clearing and the reset register always reads 0. The reset will be asserted for
15 SYSCLK cycles. Instead of writing 0 to the register, wait using ndelay.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/media/i2c/mt9v032.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/media/i2c/mt9v032.c b/drivers/media/i2c/mt9v032.c
index f04d0bb..29d8d8f 100644
--- a/drivers/media/i2c/mt9v032.c
+++ b/drivers/media/i2c/mt9v032.c
@@ -315,6 +315,7 @@ mt9v032_update_hblank(struct mt9v032 *mt9v032)
 static int mt9v032_power_on(struct mt9v032 *mt9v032)
 {
 	struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+	unsigned long rate;
 	int ret;
 
 	ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
@@ -332,9 +333,9 @@ static int mt9v032_power_on(struct mt9v032 *mt9v032)
 	if (ret < 0)
 		return ret;
 
-	ret = mt9v032_write(client, MT9V032_RESET, 0);
-	if (ret < 0)
-		return ret;
+	/* Wait 15 SYSCLK cycles, 564 ns @ 26.6 MHz */
+	rate = clk_get_rate(mt9v032->clk);
+	ndelay(DIV_ROUND_UP(15 * 125000000, rate >> 3));
 
 	return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0);
 }
-- 
2.0.0.rc2