From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition for mt8195
Date: Sat, 17 Jul 2021 17:03:59 +0800 [thread overview]
Message-ID: <20210717090408.28283-2-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20210717090408.28283-1-nancy.lin@mediatek.com>
1. Add pseudo-ovl definition file for mt8195 display.
2. Add mediatek,pseudo-ovl.yaml to decribe pseudo-ovl module in details.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 5 +
.../display/mediatek/mediatek,pseudo-ovl.yaml | 105 ++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index aac1796e3f6b..bb6d28572b48 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -230,6 +230,11 @@ properties:
- items:
- const: mediatek,mt8173-disp-od
+ # PSEUDO-OVL: see Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
+ # for details.
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+
reg:
description: Physical base address and length of the function block register space.
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
new file mode 100644
index 000000000000..9059d96ce70e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,pseudo-ovl.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,pseudo-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek pseudo ovl Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Nancy.Lin <nancy.lin@mediatek.com>
+
+description: |
+ The Mediatek pseudo ovl function block is composed of eight RDMA and
+ four MERGE devices. It's encapsulated as an overlay device, which supports
+ 4 layers.
+
+properties:
+ compatible:
+ oneOf:
+ # pseudo ovl controller
+ - items:
+ - const: mediatek,mt8195-disp-pseudo-ovl
+ # RDMA: read DMA
+ - items:
+ - const: mediatek,mt8195-vdo1-rdma
+ # MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-vdo1-merge
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+ iommus:
+ description: The compatible property is DMA function blocks.
+ Should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
+ details.
+ maxItems: 1
+ clocks:
+ maxItems: 2
+ clock-names:
+ maxItems: 2
+ power-domains:
+ maxItems: 1
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
+ display function block.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const:
+ - mediatek,mt8195-vdo1-merge
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: merge clock
+ - description: merge async clock
+ clock-names:
+ items:
+ - const: merge
+ - const: merge_async
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ vdo1_rdma@1c104000 {
+ compatible = "mediatek,mt8195-vdo1-rdma",
+ "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>;
+ };
+
+ disp_vpp_merge@1c10c000 {
+ compatible = "mediatek,mt8195-vdo1-merge";
+ reg = <0 0x1c10c000 0 0x1000>;
+ interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0xc000 0x1000>;
+ };
+
+...
--
2.18.0
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next prev parent reply other threads:[~2021-07-17 9:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-17 9:03 [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-07-17 9:03 ` Nancy.Lin [this message]
2021-07-18 23:22 ` [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition " Chun-Kuang Hu
2021-07-22 0:59 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 02/10] dt-bindings: mediatek: add ethdr " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 05/10] soc: mediatek: add mtk-mutex " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 5:25 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 07/10] drm/mediatek: add pseudo ovl " Nancy.Lin
2021-07-20 5:57 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 08/10] drm/mediatek: add merge vblank " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
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