From: Nancy.Lin <nancy.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>, <srv_heupstream@mediatek.com>
Subject: [PATCH v1 04/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
Date: Sat, 17 Jul 2021 17:04:02 +0800 [thread overview]
Message-ID: <20210717090408.28283-5-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20210717090408.28283-1-nancy.lin@mediatek.com>
Add mt8195 vdosys1 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 83 ++++++++++++++++++++++++--
drivers/soc/mediatek/mtk-mmsys.c | 10 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 73e9e8286d50..bc4e291dbe35 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -64,16 +64,16 @@
#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
-#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN1_SEL (1 << 0)
#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
-#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN2_SEL (1 << 0)
#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
-#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+#define SOUT_TO_MIXER_IN3_SEL (1 << 0)
#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
-#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+#define SOUT_TO_MIXER_IN4_SEL (1 << 0)
#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
@@ -88,7 +88,7 @@
#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
-#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+#define MIXER_SOUT_TO_MERGE4_ASYNC_SEL (1 << 0)
#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
@@ -185,6 +185,79 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}, {
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN1_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN2_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN3_SEL
+ },
+ {
+ DDP_COMPONENT_PSEUDO_OVL, DDP_COMPONENT_ETHDR,
+ MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, SOUT_TO_MIXER_IN4_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_OUT_SOUT_SEL, MIXER_SOUT_TO_MERGE4_ASYNC_SEL
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN1_SEL_IN, MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN2_SEL_IN, MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN3_SEL_IN, MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_IN4_SEL_IN, MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MIXER_SOUT_SEL_IN, MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
+ },
+ {
+ DDP_COMPONENT_ETHDR, DDP_COMPONENT_MERGE5,
+ MT8195_VDO1_MERGE4_ASYNC_SEL_IN, MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_DISP_DPI1_SEL_IN, DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DPI1_SEL
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_DISP_DP_INTF0_SEL_IN,
+ DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
+ },
+ {
+ DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
+ MT8195_VDO1_MERGE4_SOUT_SEL, MERGE4_SOUT_TO_DP_INTF0_SEL
}
};
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1fb241750897..9e31aad6c5c8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -59,6 +59,12 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+ .clk_driver = "clk-mt8195-vdo1",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -168,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys0",
.data = &mt8195_vdosys0_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys1",
+ .data = &mt8195_vdosys1_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 34cb605e5df9..f9b227a07fe6 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSC1,
DDP_COMPONENT_DSC1_VIRTUAL0,
DDP_COMPONENT_DP_INTF0,
+ DDP_COMPONENT_DP_INTF1,
+ DDP_COMPONENT_PSEUDO_OVL,
+ DDP_COMPONENT_ETHDR,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
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next prev parent reply other threads:[~2021-07-17 9:04 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-17 9:03 [PATCH v1 00/10] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-07-17 9:03 ` [PATCH v1 01/10] dt-bindings: mediatek: add pseudo-ovl definition " Nancy.Lin
2021-07-18 23:22 ` Chun-Kuang Hu
2021-07-22 0:59 ` Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 02/10] dt-bindings: mediatek: add ethdr " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 03/10] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-07-17 9:04 ` Nancy.Lin [this message]
2021-07-17 9:04 ` [PATCH v1 05/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 06/10] drm/mediatek: add ETHDR support for MT8195 Nancy.Lin
2021-07-18 23:56 ` Chun-Kuang Hu
2021-07-22 1:32 ` Nancy.Lin
2021-07-22 5:25 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 07/10] drm/mediatek: add pseudo ovl " Nancy.Lin
2021-07-20 5:57 ` CK Hu
2021-07-17 9:04 ` [PATCH v1 08/10] drm/mediatek: add merge vblank " Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 09/10] soc: mediatek: mmsys: add new mtk_mmsys struct member to store drm data Nancy.Lin
2021-07-17 9:04 ` [PATCH v1 10/10] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
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