From: "H. Nikolaus Schaller" <hns@goldelico.com>
To: "\"周琰杰 (Zhou Yanjie)\"" <zhouyanjie@wanyeetech.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, tsbogend@alpha.franken.de,
paulburton@kernel.org, jiaxun.yang@flygoat.com,
chenhc@lemote.com, tglx@linutronix.de, robh+dt@kernel.org,
daniel.lezcano@linaro.org, keescook@chromium.org,
paul@crapouillou.net, krzk@kernel.org, ebiederm@xmission.com,
dongsheng.qiu@ingenic.com, yanfei.li@ingenic.com,
rick.tyliu@ingenic.com, sernia.zhou@foxmail.com,
zhenwenjin@gmail.com
Subject: Re: [PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs.
Date: Thu, 10 Sep 2020 09:52:37 +0200 [thread overview]
Message-ID: <8EBCE2D3-8683-4E57-912F-41D03C943CC9@goldelico.com> (raw)
In-Reply-To: <1589898923-60048-7-git-send-email-zhouyanjie@wanyeetech.com>
Hi Zhou Yanjie,
what is the status of this series? It does not seem to have arrived in linux-next for v5.10-rc1.
BR and thanks,
Nikolaus
> Am 19.05.2020 um 16:35 schrieb 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>:
>
> Add 'cpus' node to the jz4740.dtsi, jz4770.dtsi, jz4780.dtsi
> and x1000.dtsi files.
>
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
>
> Notes:
> v1->v2:
> No change.
>
> v2->v3:
> No change.
>
> v3->v4:
> Rebase on top of kernel 5.6-rc1.
>
> v4->v5:
> No change.
>
> v5->v6:
> No change.
>
> v6->v7:
> Update compatible strings.
>
> v7->v8:
> No change.
>
> arch/mips/boot/dts/ingenic/jz4740.dtsi | 14 ++++++++++++++
> arch/mips/boot/dts/ingenic/jz4770.dtsi | 15 ++++++++++++++-
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 23 +++++++++++++++++++++++
> arch/mips/boot/dts/ingenic/x1000.dtsi | 14 ++++++++++++++
> 4 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi
> index a3301ba..1f2f896 100644
> --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi
> @@ -7,6 +7,20 @@
> #size-cells = <1>;
> compatible = "ingenic,jz4740";
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-mxu1.0";
> + reg = <0>;
> +
> + clocks = <&cgu JZ4740_CLK_CCLK>;
> + clock-names = "cpu";
> + };
> + };
> +
> cpuintc: interrupt-controller {
> #address-cells = <0>;
> #interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> index 0bfb9ed..12c7101 100644
> --- a/arch/mips/boot/dts/ingenic/jz4770.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> @@ -1,5 +1,4 @@
> // SPDX-License-Identifier: GPL-2.0
> -
> #include <dt-bindings/clock/jz4770-cgu.h>
>
> / {
> @@ -7,6 +6,20 @@
> #size-cells = <1>;
> compatible = "ingenic,jz4770";
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <0>;
> +
> + clocks = <&cgu JZ4770_CLK_CCLK>;
> + clock-names = "cpu";
> + };
> + };
> +
> cpuintc: interrupt-controller {
> #address-cells = <0>;
> #interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index bb89653..03aeeff 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -8,6 +8,29 @@
> #size-cells = <1>;
> compatible = "ingenic,jz4780";
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <0>;
> +
> + clocks = <&cgu JZ4780_CLK_CPU>;
> + clock-names = "cpu";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <1>;
> +
> + clocks = <&cgu JZ4780_CLK_CORE1>;
> + clock-names = "cpu";
> + };
> + };
> +
> cpuintc: interrupt-controller {
> #address-cells = <0>;
> #interrupt-cells = <1>;
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index 147f7d5..2205e1b 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -8,6 +8,20 @@
> #size-cells = <1>;
> compatible = "ingenic,x1000", "ingenic,x1000e";
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <0>;
> +
> + clocks = <&cgu X1000_CLK_CPU>;
> + clock-names = "cpu";
> + };
> + };
> +
> cpuintc: interrupt-controller {
> #address-cells = <0>;
> #interrupt-cells = <1>;
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-09-10 7:55 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 14:35 Introduce SMP support for CI20 (based on JZ4780) v8 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 0/6] Introduce SMP support for CI20 (based on JZ4780) 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-05-19 16:09 ` Paul Cercueil
2020-05-20 7:24 ` Zhou Yanjie
2020-05-19 18:21 ` kbuild test robot
2020-05-19 19:41 ` Paul Cercueil
2020-05-20 7:23 ` Zhou Yanjie
2020-05-20 11:33 ` Paul Cercueil
2020-05-20 12:32 ` Jiaxun Yang
2020-05-19 14:35 ` [PATCH v8 2/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 3/6] clocksource: Ingenic: Add high resolution timer support " 周琰杰 (Zhou Yanjie)
2020-05-19 17:42 ` Paul Cercueil
2020-05-19 20:11 ` [PATCH] " Paul Cercueil
2020-05-20 22:14 ` Paul Boddie
2020-05-22 12:26 ` Paul Cercueil
2020-05-22 19:16 ` Paul Boddie
2020-05-25 23:03 ` JZ4780 LCD controller initialisation (was Re: [PATCH] clocksource: Ingenic: Add high resolution timer support for SMP.) Paul Boddie
2020-05-26 4:48 ` H. Nikolaus Schaller
2020-05-26 15:03 ` Paul Cercueil
2020-05-26 22:44 ` Paul Boddie
2020-05-26 23:07 ` Paul Cercueil
2020-06-01 20:06 ` Paul Boddie
2020-06-23 21:28 ` Paul Boddie
2020-05-19 14:35 ` [PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding 周琰杰 (Zhou Yanjie)
2020-05-26 19:29 ` Rob Herring
2020-05-27 5:59 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-09-10 7:52 ` H. Nikolaus Schaller [this message]
2020-09-12 6:17 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 6/6] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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