Re: JZ4780 LCD controller initialisation (was Re: [PATCH] clocksource: Ingenic: Add high resolution timer support for SMP.)

[Paul Cercueil <paul@crapouillou.net>]

Hi,

Le mer. 27 mai 2020 à 0:44, Paul Boddie <paul@boddie.org.uk> a écrit :
> Paul,
> 
> Thanks for the reply!
> 
> On Tuesday 26. May 2020 17.03.04 Paul Cercueil wrote:
>> 
>>  "lcd0pixclk" and "tve" are for LCD0, "lcd1pixclk" and "lcd" are for
>>  LCD1.
> 
> The 3.0.8 kernel actually uses LCD0 for what the documentation and 
> 3.18 kernel
> call TVE, and it uses LCD1 for what the others call LCD. That earlier 
> kernel
> indicates that LCD1 is the parent clock of LCD0.
> 
> I actually found that you can enable LCD0 and not LCD1 and the LCD 
> controller
> (LCDC0) still operates to an extent, but without LCD1 enabled I 
> didn't see a
> DMA command value in the appropriate register, discussed below.

Yes, I was preparing a patch for the clock driver, then I noticed that 
too.

> [...]
> 
>>  OK, indeed the BPP and OSD config is read-only, and it's not a doc
>>  typo. How annoying.
>> 
>>  I tried to configure the LCD controller for a 8-byte descriptor 
>> without
>>  much success. No IRQs here either.
> 
> I had a look at the interrupt controller registers to see whether I 
> was
> missing anything obvious, but the mask was correctly configured to 
> unmask LCD
> interrupts (bit 31 of ICMR0). I did wonder whether the PDMA 
> interrupts might
> need unmasking, just in case there is some interaction between the 
> peripherals
> and that part of the hardware, but unmasking LCD interrupts there 
> (bit 31 of
> DMR0) didn't make any difference.
> 
> One observation I can make is that the length or size field of the 
> LCD command
> register (LCDCMD0) does get initialised to the appropriate value as 
> set in a
> descriptor. Since I don't set this register explicitly myself 
> (unlike, I
> think, the current Ingenic DRM driver in the Linux kernel), the value 
> must
> have been set up appropriately by a DMA transfer, as configured using 
> the
> descriptor address register (LCDDA0). However, the command flags I 
> also set in
> the descriptor are not reflected in the register. So, 0x44140000 
> becomes
> 0x00140000.
> 
> I thought I should check the interrupt ID register (LCDIID) to see 
> what it
> reveals. Despite setting a value in the appropriate descriptor field, 
> the
> register contains only zero.
> 
> I think I must probably tackle the job of initialising the HDMI 
> controller to
> see if that makes a difference. If the interrupts are not working but 
> are also
> not necessary, then maybe I get a visual indication of success.

Don't focus too much on interrupts right now. You don't get interrupts 
because the data is not flowing. Which in turns is caused either by the 
LCDC not being correctly configured, or the HDMI not sending 
hsync/vsync signals.

For now, what seems to be the problem is that the DMA descriptors 
aren't loaded properly. Whatever I do, the debug registers 
(LCDSAx/LCDIDx/etc) are still zero here.

-Paul