[PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Théo Lebrun]

Hi all,

V3 of this series adding octal SPI-NOR support to Mobileye EyeQ5
platform. It has been tested on EyeQ5 hardware successfully.
V1 cover letter [5] contains a brief summary of what gets added.

There is no dependency except if you want zero errors in devicetree:
system-controller series [3] for <&clocks> phandle.

Have a nice day,
Théo

[0]: https://lore.kernel.org/lkml/20240216174227.409400-1-gregory.clement@bootlin.com/
[1]: https://lore.kernel.org/linux-mips/20240209-regname-v1-0-2125efa016ef@flygoat.com/
[2]: https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git/log/
[3]: https://lore.kernel.org/lkml/20240301-mbly-clk-v9-0-cbf06eb88708@bootlin.com/
[4]: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/
[5]: https://lore.kernel.org/lkml/20240308-cdns-qspi-mbly-v1-0-a503856dd205@bootlin.com/
[6]: https://lore.kernel.org/lkml/171259906078.120310.15397790336440498713.b4-ty@kernel.org/

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
Changes in v3:
- dt-bindings:
  - Patch "sort compatibles alphabetically":
    - Moved first.
    - Take Reviewed-By Krzysztof.
  - Patch "add mobileye,eyeq5-ospi compatible":
  - EyeQ5 no longer implies no cdns,fifo-depth prop. Patch now only adds
    compatible, no more property conditional.
  - New "make cdns,fifo-depth optional" patch, for all compatibles.
- Driver:
  - FIFO depth detection is no longer a quirk. It is for all compatibles
    if no DT property is provided.
  - Rebase onto spi-next [4] to drop three patches. No-IRQ mode patch is
    mentioned in email saying a subset of patches got applied [6].
    However, it is not in spi-next, so it is kept in series.
  - Busywait is no longer behind a quirk; it applies to all compatibles.
  - No-IRQ mode patch got modified to change its quirk index because
    previous quirk got removed.
  - As we removed some quirks, we no longer overflow u8 quirks.
- Link to v2: https://lore.kernel.org/r/20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com

Changes in v2:
- Rebase upon v6.9-rc2.
- Fix dt-bindings commit subject tags.
- Take Reviewed-by: Krzysztof Kozlowski on dt-bindings commit.
- Add dt-bindings commit to order compatibles alphabetically.
  Krzysztof: unsure if you want this. It is second so that commit
  adding EyeQ5 compatible can be taken alone easily.
- Drop patch taken upstream:
  spi: cadence-qspi: switch from legacy names to modern ones
- Add To: Rob Herring, following get_maintainer.pl recommendation.
- Link to v1: https://lore.kernel.org/r/20240308-cdns-qspi-mbly-v1-0-a503856dd205@bootlin.com

---
Théo Lebrun (9):
      spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
      spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible
      spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional
      spi: cadence-qspi: allow FIFO depth detection
      spi: cadence-qspi: add no-IRQ mode to indirect reads
      spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
      spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
      MIPS: mobileye: eyeq5: Add SPI-NOR controller node
      MIPS: mobileye: eyeq5: add octal flash node to eval board DTS

 .../devicetree/bindings/spi/cdns,qspi-nor.yaml     |  8 +-
 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts         | 15 ++++
 arch/mips/boot/dts/mobileye/eyeq5.dtsi             | 15 ++++
 drivers/spi/spi-cadence-quadspi.c                  | 93 +++++++++++++++++-----
 4 files changed, 108 insertions(+), 23 deletions(-)
---
base-commit: d442072c067c86787dcee22c5d30d36b14edbba7
change-id: 20240209-cdns-qspi-mbly-de2205a44ab3

Best regards,
-- 
Théo Lebrun <theo.lebrun@bootlin.com>

[PATCH v3 1/9] spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically

[Théo Lebrun]

Compatibles are ordered by date of addition.
Switch to (deterministic) alphabetical ordering.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index cca81f89e252..b865d4cc25cc 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -68,12 +68,12 @@ properties:
       - items:
           - enum:
               - amd,pensando-elba-qspi
-              - ti,k2g-qspi
-              - ti,am654-ospi
               - intel,lgm-qspi
-              - xlnx,versal-ospi-1.0
               - intel,socfpga-qspi
               - starfive,jh7110-qspi
+              - ti,am654-ospi
+              - ti,k2g-qspi
+              - xlnx,versal-ospi-1.0
           - const: cdns,qspi-nor
       - const: cdns,qspi-nor
 

-- 
2.44.0

[PATCH v3 2/9] spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible

[Théo Lebrun]

Add Mobileye EyeQ5 compatible.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index b865d4cc25cc..587baf35e4e3 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -70,6 +70,7 @@ properties:
               - amd,pensando-elba-qspi
               - intel,lgm-qspi
               - intel,socfpga-qspi
+              - mobileye,eyeq5-ospi
               - starfive,jh7110-qspi
               - ti,am654-ospi
               - ti,k2g-qspi

-- 
2.44.0

[PATCH v3 3/9] spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional

[Théo Lebrun]

Make cdns,fifo-depth devicetree property optional.
Value can be detected at runtime.

Upper SRAMPARTITION register bits are read-only. Procedure to find FIFO
depth is therefore to write 0xFFFFFFFF and read back to get amount of
writeable bits.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
index 587baf35e4e3..d48ecd6cd5ad 100644
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -146,7 +146,6 @@ required:
   - reg
   - interrupts
   - clocks
-  - cdns,fifo-depth
   - cdns,fifo-width
   - cdns,trigger-address
   - '#address-cells'

-- 
2.44.0

Re: [PATCH v3 3/9] spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional

[Rob Herring]

On Wed, 10 Apr 2024 11:29:06 +0200, Théo Lebrun wrote:
> Make cdns,fifo-depth devicetree property optional.
> Value can be detected at runtime.
> 
> Upper SRAMPARTITION register bits are read-only. Procedure to find FIFO
> depth is therefore to write 0xFFFFFFFF and read back to get amount of
> writeable bits.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 -
>  1 file changed, 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v3 4/9] spi: cadence-qspi: allow FIFO depth detection

[Théo Lebrun]

If FIFO depth DT property is provided, check it matches what hardware
reports and warn otherwise. Else, use hardware provided value.

Hardware exposes FIFO depth indirectly because
CQSPI_REG_SRAMPARTITION is partially read-only.

Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/spi/spi-cadence-quadspi.c | 39 ++++++++++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 7 deletions(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 9896e9fe7ffb..b499f2e5ec87 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1503,6 +1503,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
 
 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
 {
+	const struct cqspi_driver_platdata *ddata = cqspi->ddata;
 	struct device *dev = &cqspi->pdev->dev;
 	struct device_node *np = dev->of_node;
 	u32 id[2];
@@ -1510,8 +1511,8 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
 	cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
 
 	if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
-		dev_err(dev, "couldn't determine fifo-depth\n");
-		return -ENXIO;
+		/* Zero signals FIFO depth should be runtime detected. */
+		cqspi->fifo_depth = 0;
 	}
 
 	if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
@@ -1541,8 +1542,6 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
 {
 	u32 reg;
 
-	cqspi_controller_enable(cqspi, 0);
-
 	/* Configure the remap address register, no remap */
 	writel(0, cqspi->iobase + CQSPI_REG_REMAP);
 
@@ -1576,8 +1575,30 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
 		reg |= CQSPI_REG_CONFIG_DMA_MASK;
 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
 	}
+}
 
-	cqspi_controller_enable(cqspi, 1);
+static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
+{
+	const struct cqspi_driver_platdata *ddata = cqspi->ddata;
+	struct device *dev = &cqspi->pdev->dev;
+	u32 reg, fifo_depth;
+
+	/*
+	 * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
+	 * the FIFO depth.
+	 */
+	writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+	reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+	fifo_depth = reg + 1;
+
+	/* FIFO depth of zero means no value from devicetree was provided. */
+	if (cqspi->fifo_depth == 0) {
+		cqspi->fifo_depth = fifo_depth;
+		dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth);
+	} else if (fifo_depth != cqspi->fifo_depth) {
+		dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n",
+			 fifo_depth, cqspi->fifo_depth);
+	}
 }
 
 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
@@ -1730,6 +1751,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	cqspi->pdev = pdev;
 	cqspi->host = host;
 	cqspi->is_jh7110 = false;
+	cqspi->ddata = ddata = of_device_get_match_data(dev);
 	platform_set_drvdata(pdev, cqspi);
 
 	/* Obtain configuration from OF. */
@@ -1821,8 +1843,6 @@ static int cqspi_probe(struct platform_device *pdev)
 	/* write completion is supported by default */
 	cqspi->wr_completion = true;
 
-	ddata = of_device_get_match_data(dev);
-	cqspi->ddata = ddata;
 	if (ddata) {
 		if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
 			cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
@@ -1864,7 +1884,10 @@ static int cqspi_probe(struct platform_device *pdev)
 	}
 
 	cqspi_wait_idle(cqspi);
+	cqspi_controller_enable(cqspi, 0);
+	cqspi_controller_detect_fifo_depth(cqspi);
 	cqspi_controller_init(cqspi);
+	cqspi_controller_enable(cqspi, 1);
 	cqspi->current_cs = -1;
 	cqspi->sclk = 0;
 
@@ -1947,7 +1970,9 @@ static int cqspi_runtime_resume(struct device *dev)
 
 	clk_prepare_enable(cqspi->clk);
 	cqspi_wait_idle(cqspi);
+	cqspi_controller_enable(cqspi, 0);
 	cqspi_controller_init(cqspi);
+	cqspi_controller_enable(cqspi, 1);
 
 	cqspi->current_cs = -1;
 	cqspi->sclk = 0;

-- 
2.44.0

Re: [PATCH v3 4/9] spi: cadence-qspi: allow FIFO depth detection

[Mark Brown]

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On Wed, Apr 10, 2024 at 11:29:07AM +0200, Théo Lebrun wrote:

> If FIFO depth DT property is provided, check it matches what hardware
> reports and warn otherwise. Else, use hardware provided value.
> 
> Hardware exposes FIFO depth indirectly because
> CQSPI_REG_SRAMPARTITION is partially read-only.

This breaks an allmodconfig build:

/build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_of_get_
pdata’:
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1506:45: error: unused vari
able ‘ddata’ [-Werror=unused-variable]
 1506 |         const struct cqspi_driver_platdata *ddata = cqspi->ddata;
      |                                             ^~~~~
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_control
ler_detect_fifo_depth’:
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1582:45: error: unused vari
able ‘ddata’ [-Werror=unused-variable]
 1582 |         const struct cqspi_driver_platdata *ddata = cqspi->ddata;
      |                                             ^~~~~
cc1: all warnings being treated as errors

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Re: [PATCH v3 4/9] spi: cadence-qspi: allow FIFO depth detection

[Théo Lebrun]

Hello,

On Wed Apr 10, 2024 at 10:03 PM CEST, Mark Brown wrote:
> On Wed, Apr 10, 2024 at 11:29:07AM +0200, Théo Lebrun wrote:
>
> > If FIFO depth DT property is provided, check it matches what hardware
> > reports and warn otherwise. Else, use hardware provided value.
> > 
> > Hardware exposes FIFO depth indirectly because
> > CQSPI_REG_SRAMPARTITION is partially read-only.
>
> This breaks an allmodconfig build:
>
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_of_get_
> pdata’:
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1506:45: error: unused vari
> able ‘ddata’ [-Werror=unused-variable]
>  1506 |         const struct cqspi_driver_platdata *ddata = cqspi->ddata;
>       |                                             ^~~~~
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_control
> ler_detect_fifo_depth’:
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1582:45: error: unused vari
> able ‘ddata’ [-Werror=unused-variable]
>  1582 |         const struct cqspi_driver_platdata *ddata = cqspi->ddata;
>       |                                             ^~~~~
> cc1: all warnings being treated as errors

I really should fix my kernel compiler warnings. Sorry about that.
Will fix next revision.

Regards,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH v3 5/9] spi: cadence-qspi: add no-IRQ mode to indirect reads

[Théo Lebrun]

Support reads through polling, without any IRQ. The main reason is
performance; profiling shows that the first IRQ comes quickly on our
specific hardware. Once this IRQ arrives, we poll until all data is
retrieved. Avoid initial sleep to reduce IRQ count.

Hide this behavior behind a quirk flag.

This is confirmed through micro-benchmarks, but also end-to-end
performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS
filesystem:
 - No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs
 - CQSPI_SLOW_SRAM,  ~10.34s, ~22.7 MB/s,  70284 IRQs
 - CQSPI_RD_NO_IRQ,   ~9.37s, ~25.1 MB/s,    521 IRQs

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/spi/spi-cadence-quadspi.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index b499f2e5ec87..cde84d10678e 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -42,6 +42,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX);
 #define CQSPI_NO_SUPPORT_WR_COMPLETION	BIT(3)
 #define CQSPI_SLOW_SRAM		BIT(4)
 #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR	BIT(5)
+#define CQSPI_RD_NO_IRQ			BIT(6)
 
 /* Capabilities */
 #define CQSPI_SUPPORTS_OCTAL		BIT(0)
@@ -702,6 +703,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 				       const size_t n_rx)
 {
 	struct cqspi_st *cqspi = f_pdata->cqspi;
+	bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ);
 	struct device *dev = &cqspi->pdev->dev;
 	void __iomem *reg_base = cqspi->iobase;
 	void __iomem *ahb_base = cqspi->ahb_base;
@@ -725,17 +727,20 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 	 * all the read interrupts disabled for max performance.
 	 */
 
-	if (!cqspi->slow_sram)
+	if (use_irq && cqspi->slow_sram)
+		writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
+	else if (use_irq)
 		writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
 	else
-		writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
+		writel(0, reg_base + CQSPI_REG_IRQMASK);
 
 	reinit_completion(&cqspi->transfer_complete);
 	writel(CQSPI_REG_INDIRECTRD_START_MASK,
 	       reg_base + CQSPI_REG_INDIRECTRD);
 
 	while (remaining > 0) {
-		if (!wait_for_completion_timeout(&cqspi->transfer_complete,
+		if (use_irq &&
+		    !wait_for_completion_timeout(&cqspi->transfer_complete,
 						 msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS)))
 			ret = -ETIMEDOUT;
 
@@ -777,7 +782,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 			bytes_to_read = cqspi_get_rd_sram_level(cqspi);
 		}
 
-		if (remaining > 0) {
+		if (use_irq && remaining > 0) {
 			reinit_completion(&cqspi->transfer_complete);
 			if (cqspi->slow_sram)
 				writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);

-- 
2.44.0

[PATCH v3 6/9] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()

[Théo Lebrun]

Call readl_relaxed_poll_timeout() with no sleep at the start of
cqspi_wait_for_bit(). If its short timeout expires, a sleeping
readl_relaxed_poll_timeout() call takes the relay.

The reason is to avoid hrtimer interrupts on the system. All read
operations are expected to take less than 100µs.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/spi/spi-cadence-quadspi.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index cde84d10678e..fecb76cfb932 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -120,6 +120,7 @@ struct cqspi_driver_platdata {
 /* Operation timeout value */
 #define CQSPI_TIMEOUT_MS			500
 #define CQSPI_READ_TIMEOUT_MS			10
+#define CQSPI_BUSYWAIT_TIMEOUT_US		500
 
 /* Runtime_pm autosuspend delay */
 #define CQSPI_AUTOSUSPEND_TIMEOUT		2000
@@ -298,13 +299,27 @@ struct cqspi_driver_platdata {
 
 #define CQSPI_REG_VERSAL_DMA_VAL		0x602
 
-static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr)
+static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata,
+			      void __iomem *reg, const u32 mask, bool clr,
+			      bool busywait)
 {
+	u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC;
 	u32 val;
 
+	if (busywait) {
+		int ret = readl_relaxed_poll_timeout(reg, val,
+						     (((clr ? ~val : val) & mask) == mask),
+						     0, CQSPI_BUSYWAIT_TIMEOUT_US);
+
+		if (ret != -ETIMEDOUT)
+			return ret;
+
+		timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US;
+	}
+
 	return readl_relaxed_poll_timeout(reg, val,
 					  (((clr ? ~val : val) & mask) == mask),
-					  10, CQSPI_TIMEOUT_MS * 1000);
+					  10, timeout_us);
 }
 
 static bool cqspi_is_idle(struct cqspi_st *cqspi)
@@ -434,8 +449,8 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);
 
 	/* Polling for completion. */
-	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
-				 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1);
+	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL,
+				 CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true);
 	if (ret) {
 		dev_err(&cqspi->pdev->dev,
 			"Flash command execution timed out.\n");
@@ -790,8 +805,8 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
 	}
 
 	/* Check indirect done status */
-	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
-				 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
+	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD,
+				 CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true);
 	if (ret) {
 		dev_err(dev, "Indirect read completion error (%i)\n", ret);
 		goto failrd;
@@ -1091,8 +1106,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
 	}
 
 	/* Check indirect done status */
-	ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
-				 CQSPI_REG_INDIRECTWR_DONE_MASK, 0);
+	ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR,
+				 CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false);
 	if (ret) {
 		dev_err(dev, "Indirect write completion error (%i)\n", ret);
 		goto failwr;

-- 
2.44.0

[PATCH v3 7/9] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible

[Théo Lebrun]

Declare a new mobileye,eyeq5-ospi compatible.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/spi/spi-cadence-quadspi.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index fecb76cfb932..7a287b329728 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2057,6 +2057,12 @@ static const struct cqspi_driver_platdata pensando_cdns_qspi = {
 	.quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE,
 };
 
+static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = {
+	.hwcaps_mask = CQSPI_SUPPORTS_OCTAL,
+	.quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION |
+			CQSPI_RD_NO_IRQ,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
 	{
 		.compatible = "cdns,qspi-nor",
@@ -2090,6 +2096,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
 		.compatible = "amd,pensando-elba-qspi",
 		.data = &pensando_cdns_qspi,
 	},
+	{
+		.compatible = "mobileye,eyeq5-ospi",
+		.data = &mobileye_eyeq5_ospi,
+	},
 	{ /* end of table */ }
 };
 

-- 
2.44.0

[PATCH v3 8/9] MIPS: mobileye: eyeq5: Add SPI-NOR controller node

[Théo Lebrun]

Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree.
Octal is supported.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 8d4f65ec912d..1543c2b9bcb6 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -158,6 +158,21 @@ timer {
 				clocks = <&core0_clk>;
 			};
 		};
+
+		ospi: spi@2100000 {
+			compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
+			reg = <0 0x2100000 0x0 0x1000>,
+			      <0 0x10000000 0x0 0x8000000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks EQ5C_DIV_OSPI>;
+			assigned-clocks = <&clocks EQ5C_DIV_OSPI>;
+			assigned-clock-rates = <167000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x00000000>;
+		};
 	};
 };
 

-- 
2.44.0

[PATCH v3 9/9] MIPS: mobileye: eyeq5: add octal flash node to eval board DTS

[Théo Lebrun]

Add SPI-NOR octal flash node to evaluation board devicetree.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
index 6898b2d8267d..0e5fee7b680c 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
@@ -21,3 +21,18 @@ memory@0 {
 		      <0x8 0x02000000 0x0 0x7E000000>;
 	};
 };
+
+&ospi {
+	flash0: flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>; /* chip select */
+
+		spi-max-frequency = <40000000>;
+		spi-rx-bus-width = <8>;
+		cdns,read-delay = <1>;
+		cdns,tshsl-ns = <400>;
+		cdns,tsd2d-ns = <400>;
+		cdns,tchsh-ns = <125>;
+		cdns,tslch-ns = <50>;
+	};
+};

-- 
2.44.0

Re: [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Mark Brown]

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On Wed, Apr 10, 2024 at 11:29:03AM +0200, Théo Lebrun wrote:

> V1 cover letter [5] contains a brief summary of what gets added.

Please make your cover letters stand alone things, things like a basic
description of the contents of the series should just be included
directly.

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Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Mark Brown]

On Wed, 10 Apr 2024 11:29:03 +0200, Théo Lebrun wrote:
> V3 of this series adding octal SPI-NOR support to Mobileye EyeQ5
> platform. It has been tested on EyeQ5 hardware successfully.
> V1 cover letter [5] contains a brief summary of what gets added.
> 
> There is no dependency except if you want zero errors in devicetree:
> system-controller series [3] for <&clocks> phandle.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/9] spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
      commit: 002514d91fccde2adbe750c9ec5c6207d56c890b
[2/9] spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible
      commit: 52826aee484b3ebb6ed94c1ae89c0944110ed8b1
[3/9] spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional
      commit: eb4fdb4bf46f875eac3c093f7ff43a223985f7b8
[4/9] spi: cadence-qspi: allow FIFO depth detection
      (no commit info)
[5/9] spi: cadence-qspi: add no-IRQ mode to indirect reads
      (no commit info)
[6/9] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
      (no commit info)
[7/9] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
      (no commit info)

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Théo Lebrun]

Hello Mark,

On Thu Apr 11, 2024 at 2:03 PM CEST, Mark Brown wrote:
> On Wed, 10 Apr 2024 11:29:03 +0200, Théo Lebrun wrote:
> > V3 of this series adding octal SPI-NOR support to Mobileye EyeQ5
> > platform. It has been tested on EyeQ5 hardware successfully.
> > V1 cover letter [5] contains a brief summary of what gets added.
> > 
> > There is no dependency except if you want zero errors in devicetree:
> > system-controller series [3] for <&clocks> phandle.
> > 
> > [...]
>
> Applied to
>
>    https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
>
> Thanks!
>
> [1/9] spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
>       commit: 002514d91fccde2adbe750c9ec5c6207d56c890b
> [2/9] spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible
>       commit: 52826aee484b3ebb6ed94c1ae89c0944110ed8b1
> [3/9] spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional
>       commit: eb4fdb4bf46f875eac3c093f7ff43a223985f7b8
> [4/9] spi: cadence-qspi: allow FIFO depth detection
>       (no commit info)
> [5/9] spi: cadence-qspi: add no-IRQ mode to indirect reads
>       (no commit info)
> [6/9] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit()
>       (no commit info)
> [7/9] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible
>       (no commit info)

All commits tagged "(no commit info)" do not show up in your for-next
branch. Is that expected and is there anything I can do? There was one
pending -Wunused-variable compiler warning to be addressed for
example, see [0].

⟩ git log --oneline --author theo.lebrun v6.9-rc1..spi/for-next
eb4fdb4bf46f spi: dt-bindings: cdns,qspi-nor: make cdns,fifo-depth optional
52826aee484b spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible
002514d91fcc spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically
563f8598cbc2 spi: cadence-qspi: minimise register accesses on each op if !DTR
dcc594aef1bf spi: cadence-qspi: store device data pointer in private struct
708eafeba9ee spi: cadence-qspi: allow building for MIPS

[0]: https://lore.kernel.org/lkml/161eebc1-9417-4ab0-ad8c-c1b17be119b4@sirena.org.uk/

Thanks,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Mark Brown]

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On Mon, Apr 22, 2024 at 06:52:47PM +0200, Théo Lebrun wrote:

> All commits tagged "(no commit info)" do not show up in your for-next
> branch. Is that expected and is there anything I can do? There was one
> pending -Wunused-variable compiler warning to be addressed for
> example, see [0].

Please submit any patches you'd like to see included.  If there were
outstanding issues that need fixing then fixing those prior to
submitting would be sensible.

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Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Théo Lebrun]

Hello,

On Tue Apr 23, 2024 at 7:00 AM CEST, Mark Brown wrote:
> On Mon, Apr 22, 2024 at 06:52:47PM +0200, Théo Lebrun wrote:
> > All commits tagged "(no commit info)" do not show up in your for-next
> > branch. Is that expected and is there anything I can do? There was one
> > pending -Wunused-variable compiler warning to be addressed for
> > example, see [0].
>
> Please submit any patches you'd like to see included.  If there were
> outstanding issues that need fixing then fixing those prior to
> submitting would be sensible.

Seeing "Applied" followed by a list of commits, with some of those not
being applied confused me.

You received the latest revision!
https://lore.kernel.org/lkml/20240423-cdns-qspi-mbly-v4-0-3d2a7b535ad0@bootlin.com/

Thanks,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Krzysztof Kozlowski]

On 23/04/2024 12:04, Théo Lebrun wrote:
> Hello,
> 
> On Tue Apr 23, 2024 at 7:00 AM CEST, Mark Brown wrote:
>> On Mon, Apr 22, 2024 at 06:52:47PM +0200, Théo Lebrun wrote:
>>> All commits tagged "(no commit info)" do not show up in your for-next
>>> branch. Is that expected and is there anything I can do? There was one
>>> pending -Wunused-variable compiler warning to be addressed for
>>> example, see [0].
>>
>> Please submit any patches you'd like to see included.  If there were
>> outstanding issues that need fixing then fixing those prior to
>> submitting would be sensible.
> 
> Seeing "Applied" followed by a list of commits, with some of those not
> being applied confused me.

That's a standard output of b4 and maybe also Patchwork, if some parts
are applied.

Best regards,
Krzysztof

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Théo Lebrun]

Hello,

On Tue Apr 23, 2024 at 12:25 PM CEST, Krzysztof Kozlowski wrote:
> On 23/04/2024 12:04, Théo Lebrun wrote:
> > Hello,
> > 
> > On Tue Apr 23, 2024 at 7:00 AM CEST, Mark Brown wrote:
> >> On Mon, Apr 22, 2024 at 06:52:47PM +0200, Théo Lebrun wrote:
> >>> All commits tagged "(no commit info)" do not show up in your for-next
> >>> branch. Is that expected and is there anything I can do? There was one
> >>> pending -Wunused-variable compiler warning to be addressed for
> >>> example, see [0].
> >>
> >> Please submit any patches you'd like to see included.  If there were
> >> outstanding issues that need fixing then fixing those prior to
> >> submitting would be sensible.
> > 
> > Seeing "Applied" followed by a list of commits, with some of those not
> > being applied confused me.
>
> That's a standard output of b4 and maybe also Patchwork, if some parts
> are applied.

Thanks for the pointer. I've created an issue over at b4 to see what
people think about this matter. Current behavior is not intuitive as a
young contributor.

See: https://github.com/mricon/b4/issues/26

Regards,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Conor Dooley]

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On Tue, Apr 23, 2024 at 03:08:05PM +0200, Théo Lebrun wrote:
> Hello,
> 
> On Tue Apr 23, 2024 at 12:25 PM CEST, Krzysztof Kozlowski wrote:
> > On 23/04/2024 12:04, Théo Lebrun wrote:
> > > Hello,
> > > 
> > > On Tue Apr 23, 2024 at 7:00 AM CEST, Mark Brown wrote:
> > >> On Mon, Apr 22, 2024 at 06:52:47PM +0200, Théo Lebrun wrote:
> > >>> All commits tagged "(no commit info)" do not show up in your for-next
> > >>> branch. Is that expected and is there anything I can do? There was one
> > >>> pending -Wunused-variable compiler warning to be addressed for
> > >>> example, see [0].
> > >>
> > >> Please submit any patches you'd like to see included.  If there were
> > >> outstanding issues that need fixing then fixing those prior to
> > >> submitting would be sensible.
> > > 
> > > Seeing "Applied" followed by a list of commits, with some of those not
> > > being applied confused me.
> >
> > That's a standard output of b4 and maybe also Patchwork, if some parts
> > are applied.
> 
> Thanks for the pointer. I've created an issue over at b4 to see what
> people think about this matter. Current behavior is not intuitive as a
> young contributor.

FWIW, given I see `having a more confident comment such as
"(commit not applied)".` there, having (no commit info) doesn't mean
that it wasn't applied always. Sometimes I've found that due to changes
in the patch b4 could not detect that it was applied and reported (no
commit info).

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Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Mark Brown]

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On Tue, Apr 23, 2024 at 06:23:16PM +0100, Conor Dooley wrote:
> On Tue, Apr 23, 2024 at 03:08:05PM +0200, Théo Lebrun wrote:

> > Thanks for the pointer. I've created an issue over at b4 to see what
> > people think about this matter. Current behavior is not intuitive as a
> > young contributor.

> FWIW, given I see `having a more confident comment such as
> "(commit not applied)".` there, having (no commit info) doesn't mean
> that it wasn't applied always. Sometimes I've found that due to changes
> in the patch b4 could not detect that it was applied and reported (no
> commit info).

Right, it can't prove a negative - if it can't find the patch it could
be because it wasn't sent against current code and got changed
sufficiently in application to cause issues.

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Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Konstantin Ryabitsev]

On Wed, Apr 24, 2024 at 10:01:56AM +0900, Mark Brown wrote:
> > > Thanks for the pointer. I've created an issue over at b4 to see what
> > > people think about this matter. Current behavior is not intuitive as a
> > > young contributor.
> 
> > FWIW, given I see `having a more confident comment such as
> > "(commit not applied)".` there, having (no commit info) doesn't mean
> > that it wasn't applied always. Sometimes I've found that due to changes
> > in the patch b4 could not detect that it was applied and reported (no
> > commit info).
> 
> Right, it can't prove a negative - if it can't find the patch it could
> be because it wasn't sent against current code and got changed
> sufficiently in application to cause issues.

We can also be a bit more relaxed. For example, we can look at 
consecutive commits and compare the subjects to see if there's a match.  
I'll see if that's something I can add in.

In general, though, I prefer to push people in a different direction -- 
we really shouldn't be fixing up people's patches, because this 
misattributes the code to the wrong author. Instead, we really should 
either ask senders to send an updated revision, or make the changes in 
merge commits instead.

Merge commits can be created using "b4 shazam -M", but I must admit that 
editing the contents of the merge commit isn't really that 
straightforward, unfortunately.

-K

Re: (subset) [PATCH v3 0/9] spi: cadence-qspi: add Mobileye EyeQ5 support

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 516 bytes --]

On Wed, Apr 24, 2024 at 03:53:03PM -0400, Konstantin Ryabitsev wrote:

> In general, though, I prefer to push people in a different direction -- 
> we really shouldn't be fixing up people's patches, because this 
> misattributes the code to the wrong author. Instead, we really should 
> either ask senders to send an updated revision, or make the changes in 
> merge commits instead.

I don't do that - if this triggers with any of my stuff it's either that
the patch was dropped or git am did something.

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