linux-mips.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Alexander Lobakin <aleksander.lobakin@intel.com>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: <linux-mips@vger.kernel.org>, <tsbogend@alpha.franken.de>,
	<philmd@linaro.org>
Subject: Re: [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature
Date: Mon, 6 Mar 2023 15:28:02 +0100	[thread overview]
Message-ID: <b09d488f-ba4c-dba3-e2ee-87b5660dbdda@intel.com> (raw)
In-Reply-To: <20230304221524.47160-5-jiaxun.yang@flygoat.com>

From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: Sat,  4 Mar 2023 22:15:16 +0000

> Octeon has a different cache interface with traditional R4K one,
> just opt-out this flag for octeon to avoid run R4K cache initialization
> code accidentally.
> 
> Also remove ISA level assumption for 4k cache.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/include/asm/cpu-features.h | 2 +-
>  arch/mips/kernel/cpu-probe.c         | 2 ++
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
> index c0983130a44c..c613426b0bfc 100644
> --- a/arch/mips/include/asm/cpu-features.h
> +++ b/arch/mips/include/asm/cpu-features.h
> @@ -118,7 +118,7 @@
>  #define cpu_has_3k_cache	__isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
>  #endif
>  #ifndef cpu_has_4k_cache
> -#define cpu_has_4k_cache	__isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
> +#define cpu_has_4k_cache	__opt(MIPS_CPU_4K_CACHE)

This breaks compile-time optimization for this feature => hurts
performance on non-Octeon machines. Could this be done some other way?
E.g. could this be defined depending on
CONFIG_SYS_HAS_CPU_OCTEON_WHATEVER? Via its own cpu-features.h or here,
that's the second question. So that the platforms which 100% can't have
this family of CPUs wouldn't get affected.


>  #endif
>  #ifndef cpu_has_octeon_cache
>  #define cpu_has_octeon_cache	0
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 7ddf07f255f3..6d15a398d389 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
>  static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
>  {
>  	decode_configs(c);
> +	/* Octeon has different cache interface */
> +	c->options &= ~MIPS_CPU_4K_CACHE;
>  	switch (c->processor_id & PRID_IMP_MASK) {
>  	case PRID_IMP_CAVIUM_CN38XX:
>  	case PRID_IMP_CAVIUM_CN31XX:

Thanks,
Olek

  reply	other threads:[~2023-03-06 14:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-04 22:15 [PATCH 00/12] MIPS Virt board support Jiaxun Yang
2023-03-04 22:15 ` [PATCH 01/12] MIPS: Move declaration of bcache ops to cache.c Jiaxun Yang
2023-03-04 22:15 ` [PATCH 02/12] MIPS: smp-cps: Disable coherence setup for unsupported ISA Jiaxun Yang
2023-03-04 22:15 ` [PATCH 03/12] MIPS: mips-cm: Check availability of config registers Jiaxun Yang
2023-03-04 22:15 ` [PATCH 04/12] MIPS: Octeon: Opt-out 4k_cache feature Jiaxun Yang
2023-03-06 14:28   ` Alexander Lobakin [this message]
2023-03-06 19:55     ` Jiaxun Yang
2023-03-07 16:51       ` Alexander Lobakin
2023-03-04 22:15 ` [PATCH 05/12] MIPS: cpu-features: Enable octeon_cache by cpu_type Jiaxun Yang
2023-03-04 22:15 ` [PATCH 06/12] MIPS: c-octeon: Provide alternative SMP cache flush function Jiaxun Yang
2023-03-05  8:41   ` Sergei Shtylyov
2023-03-04 22:15 ` [PATCH 07/12] MIPS: Octeon: Allow CVMSEG to be disabled Jiaxun Yang
2023-03-04 22:15 ` [PATCH 08/12] MIPS: Loongson: Move arch cflags to MIPS top level Makefile Jiaxun Yang
2023-03-04 22:15 ` [PATCH 09/12] MIPS: Loongson: Don't select platform features with CPU Jiaxun Yang
2023-03-04 22:15 ` [PATCH 10/12] MIPS: Octeon: Disable CVMSEG by default on other platforms Jiaxun Yang
2023-03-04 22:15 ` [PATCH 11/12] MIPS: Add board config for virt board Jiaxun Yang
2023-03-04 22:15 ` [PATCH 12/12] MIPS: generic: Enable all CPUs supported by virt board in Kconfig Jiaxun Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b09d488f-ba4c-dba3-e2ee-87b5660dbdda@intel.com \
    --to=aleksander.lobakin@intel.com \
    --cc=jiaxun.yang@flygoat.com \
    --cc=linux-mips@vger.kernel.org \
    --cc=philmd@linaro.org \
    --cc=tsbogend@alpha.franken.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).