* [linux-next:master 7919/8897] drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2608:13: error: 'struct pipe_ctx' has no member named 'ttu_regs'
@ 2021-03-31 13:34 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2021-03-31 13:34 UTC (permalink / raw)
To: Wesley Chalmers
Cc: kbuild-all, Linux Memory Management List, Alex Deucher, Tony Cheng
[-- Attachment #1: Type: text/plain, Size: 12688 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: 7a43c78d0573e0bbbb0456b033e2b9a895b89464
commit: 752106f5c5cd10790419c9d55ac7d931652f95bf [7919/8897] drm/amd/display: Set max TTU on DPG enable
config: arc-allyesconfig (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=752106f5c5cd10790419c9d55ac7d931652f95bf
git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
git fetch --no-tags linux-next master
git checkout 752106f5c5cd10790419c9d55ac7d931652f95bf
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Note: the linux-next/master HEAD 7a43c78d0573e0bbbb0456b033e2b9a895b89464 builds fine.
It may have been fixed somewhere.
All errors (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c: In function 'commit_planes_for_stream':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2608:13: error: 'struct pipe_ctx' has no member named 'ttu_regs'
2608 | odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
| ^~
vim +2608 drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c
2553
2554 static void commit_planes_for_stream(struct dc *dc,
2555 struct dc_surface_update *srf_updates,
2556 int surface_count,
2557 struct dc_stream_state *stream,
2558 struct dc_stream_update *stream_update,
2559 enum surface_update_type update_type,
2560 struct dc_state *context)
2561 {
2562 int i, j;
2563 struct pipe_ctx *top_pipe_to_program = NULL;
2564
2565 if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
2566 /* Optimize seamless boot flag keeps clocks and watermarks high until
2567 * first flip. After first flip, optimization is required to lower
2568 * bandwidth. Important to note that it is expected UEFI will
2569 * only light up a single display on POST, therefore we only expect
2570 * one stream with seamless boot flag set.
2571 */
2572 if (stream->apply_seamless_boot_optimization) {
2573 stream->apply_seamless_boot_optimization = false;
2574
2575 if (get_seamless_boot_stream_count(context) == 0)
2576 dc->optimized_required = true;
2577 }
2578 }
2579
2580 if (update_type == UPDATE_TYPE_FULL) {
2581 #if defined(CONFIG_DRM_AMD_DC_DCN)
2582 dc_allow_idle_optimizations(dc, false);
2583
2584 #endif
2585 if (get_seamless_boot_stream_count(context) == 0)
2586 dc->hwss.prepare_bandwidth(dc, context);
2587
2588 context_clock_trace(dc, context);
2589 }
2590
2591 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2592 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2593
2594 if (!pipe_ctx->top_pipe &&
2595 !pipe_ctx->prev_odm_pipe &&
2596 pipe_ctx->stream &&
2597 pipe_ctx->stream == stream) {
2598 top_pipe_to_program = pipe_ctx;
2599 }
2600 }
2601
2602 if (stream->test_pattern.type != DP_TEST_PATTERN_VIDEO_MODE) {
2603 struct pipe_ctx *mpcc_pipe;
2604 struct pipe_ctx *odm_pipe;
2605
2606 for (mpcc_pipe = top_pipe_to_program; mpcc_pipe; mpcc_pipe = mpcc_pipe->bottom_pipe)
2607 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
> 2608 odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU;
2609 }
2610
2611
2612 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2613 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2614 if (should_use_dmub_lock(stream->link)) {
2615 union dmub_hw_lock_flags hw_locks = { 0 };
2616 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2617
2618 hw_locks.bits.lock_dig = 1;
2619 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2620
2621 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2622 true,
2623 &hw_locks,
2624 &inst_flags);
2625 } else
2626 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
2627 top_pipe_to_program->stream_res.tg);
2628 }
2629
2630 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2631 dc->hwss.interdependent_update_lock(dc, context, true);
2632 else
2633 /* Lock the top pipe while updating plane addrs, since freesync requires
2634 * plane addr update event triggers to be synchronized.
2635 * top_pipe_to_program is expected to never be NULL
2636 */
2637 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
2638
2639 // Stream updates
2640 if (stream_update)
2641 commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
2642
2643 if (surface_count == 0) {
2644 /*
2645 * In case of turning off screen, no need to program front end a second time.
2646 * just return after program blank.
2647 */
2648 if (dc->hwss.apply_ctx_for_surface)
2649 dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
2650 if (dc->hwss.program_front_end_for_ctx)
2651 dc->hwss.program_front_end_for_ctx(dc, context);
2652
2653 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2654 dc->hwss.interdependent_update_lock(dc, context, false);
2655 else
2656 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2657
2658 dc->hwss.post_unlock_program_front_end(dc, context);
2659 return;
2660 }
2661
2662 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2663 for (i = 0; i < surface_count; i++) {
2664 struct dc_plane_state *plane_state = srf_updates[i].surface;
2665 /*set logical flag for lock/unlock use*/
2666 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2667 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2668 if (!pipe_ctx->plane_state)
2669 continue;
2670 if (pipe_ctx->plane_state != plane_state)
2671 continue;
2672 plane_state->triplebuffer_flips = false;
2673 if (update_type == UPDATE_TYPE_FAST &&
2674 dc->hwss.program_triplebuffer != NULL &&
2675 !plane_state->flip_immediate && dc->debug.enable_tri_buf) {
2676 /*triple buffer for VUpdate only*/
2677 plane_state->triplebuffer_flips = true;
2678 }
2679 }
2680 }
2681 }
2682
2683 // Update Type FULL, Surface updates
2684 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2685 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2686
2687 if (!pipe_ctx->top_pipe &&
2688 !pipe_ctx->prev_odm_pipe &&
2689 pipe_ctx->stream &&
2690 pipe_ctx->stream == stream) {
2691 struct dc_stream_status *stream_status = NULL;
2692
2693 if (!pipe_ctx->plane_state)
2694 continue;
2695
2696 /* Full fe update*/
2697 if (update_type == UPDATE_TYPE_FAST)
2698 continue;
2699
2700 ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
2701
2702 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2703 /*turn off triple buffer for full update*/
2704 dc->hwss.program_triplebuffer(
2705 dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
2706 }
2707 stream_status =
2708 stream_get_status(context, pipe_ctx->stream);
2709
2710 if (dc->hwss.apply_ctx_for_surface)
2711 dc->hwss.apply_ctx_for_surface(
2712 dc, pipe_ctx->stream, stream_status->plane_count, context);
2713 }
2714 }
2715 if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
2716 dc->hwss.program_front_end_for_ctx(dc, context);
2717 #ifdef CONFIG_DRM_AMD_DC_DCN
2718 if (dc->debug.validate_dml_output) {
2719 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2720 struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
2721 if (cur_pipe.stream == NULL)
2722 continue;
2723
2724 cur_pipe.plane_res.hubp->funcs->validate_dml_output(
2725 cur_pipe.plane_res.hubp, dc->ctx,
2726 &context->res_ctx.pipe_ctx[i].rq_regs,
2727 &context->res_ctx.pipe_ctx[i].dlg_regs,
2728 &context->res_ctx.pipe_ctx[i].ttu_regs);
2729 }
2730 }
2731 #endif
2732 }
2733
2734 // Update Type FAST, Surface updates
2735 if (update_type == UPDATE_TYPE_FAST) {
2736 if (dc->hwss.set_flip_control_gsl)
2737 for (i = 0; i < surface_count; i++) {
2738 struct dc_plane_state *plane_state = srf_updates[i].surface;
2739
2740 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2741 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2742
2743 if (pipe_ctx->stream != stream)
2744 continue;
2745
2746 if (pipe_ctx->plane_state != plane_state)
2747 continue;
2748
2749 // GSL has to be used for flip immediate
2750 dc->hwss.set_flip_control_gsl(pipe_ctx,
2751 plane_state->flip_immediate);
2752 }
2753 }
2754 /* Perform requested Updates */
2755 for (i = 0; i < surface_count; i++) {
2756 struct dc_plane_state *plane_state = srf_updates[i].surface;
2757
2758 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2759 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2760
2761 if (pipe_ctx->stream != stream)
2762 continue;
2763
2764 if (pipe_ctx->plane_state != plane_state)
2765 continue;
2766 /*program triple buffer after lock based on flip type*/
2767 if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
2768 /*only enable triplebuffer for fast_update*/
2769 dc->hwss.program_triplebuffer(
2770 dc, pipe_ctx, plane_state->triplebuffer_flips);
2771 }
2772 if (srf_updates[i].flip_addr)
2773 dc->hwss.update_plane_addr(dc, pipe_ctx);
2774 }
2775 }
2776 }
2777
2778 if ((update_type != UPDATE_TYPE_FAST) && dc->hwss.interdependent_update_lock)
2779 dc->hwss.interdependent_update_lock(dc, context, false);
2780 else
2781 dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
2782
2783 if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
2784 if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {
2785 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2786 top_pipe_to_program->stream_res.tg,
2787 CRTC_STATE_VACTIVE);
2788 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2789 top_pipe_to_program->stream_res.tg,
2790 CRTC_STATE_VBLANK);
2791 top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
2792 top_pipe_to_program->stream_res.tg,
2793 CRTC_STATE_VACTIVE);
2794
2795 if (stream && should_use_dmub_lock(stream->link)) {
2796 union dmub_hw_lock_flags hw_locks = { 0 };
2797 struct dmub_hw_lock_inst_flags inst_flags = { 0 };
2798
2799 hw_locks.bits.lock_dig = 1;
2800 inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
2801
2802 dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
2803 false,
2804 &hw_locks,
2805 &inst_flags);
2806 } else
2807 top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
2808 top_pipe_to_program->stream_res.tg);
2809 }
2810
2811 if (update_type != UPDATE_TYPE_FAST)
2812 dc->hwss.post_unlock_program_front_end(dc, context);
2813
2814 // Fire manual trigger only when bottom plane is flipped
2815 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2816 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
2817
2818 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
2819 !pipe_ctx->stream || pipe_ctx->stream != stream ||
2820 !pipe_ctx->plane_state->update_flags.bits.addr_update)
2821 continue;
2822
2823 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
2824 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
2825 }
2826 }
2827
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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2021-03-31 13:34 [linux-next:master 7919/8897] drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2608:13: error: 'struct pipe_ctx' has no member named 'ttu_regs' kernel test robot
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