From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org
Cc: will@kernel.org, Vincenzo.Frascino@arm.com,
Szabolcs.Nagy@arm.com, Richard.Earnshaw@arm.com,
kevin.brodsky@arm.com, andreyknvl@google.com, pcc@google.com,
linux-mm@kvack.org, linux-arch@vger.kernel.org,
Rob.Herring@arm.com, mark.rutland@arm.com
Subject: Re: [PATCH v3 21/23] arm64: mte: Check the DT memory nodes for MTE support
Date: Mon, 27 Apr 2020 12:14:42 +0100 [thread overview]
Message-ID: <43762365-60f6-e271-1338-795e8d7fbb72@arm.com> (raw)
In-Reply-To: <20200424161742.GE5551@gaia>
Hi Catalin,
On 04/24/2020 05:17 PM, Catalin Marinas wrote:
> On Fri, Apr 24, 2020 at 02:57:36PM +0100, Catalin Marinas wrote:
>> On Tue, Apr 21, 2020 at 03:26:01PM +0100, Catalin Marinas wrote:
>>> Even if the ID_AA64PFR1_EL1 register advertises the presence of MTE, it
>>> is not guaranteed that the memory system on the SoC supports the
>>> feature. In the absence of system-wide MTE support, the behaviour is
>>> undefined and the kernel should not enable the MTE memory type in
>>> MAIR_EL1.
>>>
>>> For FDT, add an 'arm,armv8.5-memtag' property to the /memory nodes and
>>> check for its presence during MTE probing. For example:
>>>
>>> memory@80000000 {
>>> device_type = "memory";
>>> arm,armv8.5-memtag;
>>> reg = <0x00000000 0x80000000 0 0x80000000>,
>>> <0x00000008 0x80000000 0 0x80000000>;
>>> };
>>>
>>> If the /memory nodes are not present in DT or if at least one node does
>>> not support MTE, the feature will be disabled. On EFI systems, it is
>>> assumed that the memory description matches the EFI memory map (if not,
>>> it is considered a firmware bug).
>>>
>>> MTE is not currently supported on ACPI systems.
>>>
>>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Rob Herring <Rob.Herring@arm.com>
>>> Cc: Mark Rutland <mark.rutland@arm.com>
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
>>
>> This patch turns out to be incomplete. While it does not expose the
>> HWCAP2_MTE to user when the above DT property is not present, it still
>> allows user access to the ID_AA64PFR1_EL1.MTE field (via MRS emulations)
>> since it is marked as visible.
>
> Attempt below at moving the check to the CPUID fields setup. This way we
> can avoid the original patch entirely since the sanitised id regs will
> have a zero MTE field if DT doesn't support it.
>
> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
> index afc315814563..0a24d36bf231 100644
> --- a/arch/arm64/include/asm/cpufeature.h
> +++ b/arch/arm64/include/asm/cpufeature.h
> @@ -61,6 +61,7 @@ struct arm64_ftr_bits {
> u8 shift;
> u8 width;
> s64 safe_val; /* safe value for FTR_EXACT features */
> + s64 (*filter)(const struct arm64_ftr_bits *, s64);
> };
>
> /*
> @@ -542,7 +543,10 @@ cpuid_feature_extract_field(u64 features, int field, bool sign)
>
> static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
> {
> - return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
> + s64 fval = (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
> + if (ftrp->filter)
> + fval = ftrp->filter(ftrp, fval);
> + return fval;
> }
>
This change makes sure that the sanitised infrastructure is initialised
with masked value and all consumers see a "sanitised" value, including
KVM (unless they emulate it directly on the local CPU)
>
> +#ifdef CONFIG_ARM64_MTE
> +s64 mte_ftr_filter(const struct arm64_ftr_bits *ftrp, s64 val)
> +{
> + struct device_node *np;
> + static bool memory_checked = false;
> + static bool mte_capable = true;
> +
> + /* EL0-only MTE is not supported by Linux, don't expose it */
> + if (val < ID_AA64PFR1_MTE)
> + return ID_AA64PFR1_MTE_NI;
> +
> + if (memory_checked)
> + return mte_capable ? val : ID_AA64PFR1_MTE_NI;
> +
> + if (!acpi_disabled) {
> + pr_warn("MTE not supported on ACPI systems\n");
> + return ID_AA64PFR1_MTE_NI;
> + }
> +
> + /* check the DT "memory" nodes for MTE support */
> + for_each_node_by_type(np, "memory") {
> + memory_checked = true;
> + mte_capable &= of_property_read_bool(np, "arm,armv8.5-memtag");
> + }
> +
> + if (!memory_checked || !mte_capable) {
> + pr_warn("System memory is not MTE-capable\n");
> + memory_checked = true;
> + mte_capable = false;
> + return ID_AA64PFR1_MTE_NI;
> + }
> +
> + return val;
> +}
> +#endif
> +
> /*
> * NOTE: Any changes to the visibility of features should be kept in
> * sync with the documentation of the CPU feature register ABI.
> @@ -184,8 +225,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
>
> static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
> - ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
> - FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
> +#ifdef CONFIG_ARM64_MTE
> + FILTERED_ARM64_FTR_BITS(FTR_UNSIGNED, FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
> + ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI, mte_ftr_filter),
> +#endif
> ARM64_FTR_END,
> };
>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
next prev parent reply other threads:[~2020-04-27 11:09 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-21 14:25 [PATCH v3 00/23] arm64: Memory Tagging Extension user-space support Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 01/23] arm64: alternative: Allow alternative_insn to always issue the first instruction Catalin Marinas
2020-04-27 16:57 ` Dave Martin
2020-04-28 11:43 ` Catalin Marinas
2020-04-29 10:26 ` Dave Martin
2020-04-29 14:04 ` Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 02/23] arm64: mte: system register definitions Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 03/23] arm64: mte: CPU feature detection and initial sysreg configuration Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 04/23] arm64: mte: Use Normal Tagged attributes for the linear map Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 05/23] arm64: mte: Assembler macros and default architecture for .S files Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 06/23] arm64: mte: Tags-aware clear_page() implementation Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 07/23] arm64: mte: Tags-aware copy_page() implementation Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 08/23] arm64: Tags-aware memcmp_pages() implementation Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 09/23] arm64: mte: Add specific SIGSEGV codes Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 10/23] arm64: mte: Handle synchronous and asynchronous tag check faults Catalin Marinas
2020-04-23 10:38 ` Catalin Marinas
2020-04-27 16:58 ` Dave Martin
2020-04-28 13:43 ` Catalin Marinas
2020-04-29 10:26 ` Dave Martin
2020-04-21 14:25 ` [PATCH v3 11/23] mm: Introduce arch_calc_vm_flag_bits() Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 12/23] arm64: mte: Add PROT_MTE support to mmap() and mprotect() Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 13/23] mm: Introduce arch_validate_flags() Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 14/23] arm64: mte: Validate the PROT_MTE request via arch_validate_flags() Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 15/23] mm: Allow arm64 mmap(PROT_MTE) on RAM-based files Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 16/23] arm64: mte: Allow user control of the tag check mode via prctl() Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 17/23] arm64: mte: Allow user control of the generated random tags " Catalin Marinas
2020-04-21 14:25 ` [PATCH v3 18/23] arm64: mte: Restore the GCR_EL1 register after a suspend Catalin Marinas
2020-04-23 15:23 ` Lorenzo Pieralisi
2020-04-21 14:25 ` [PATCH v3 19/23] arm64: mte: Add PTRACE_{PEEK,POKE}MTETAGS support Catalin Marinas
2020-04-24 23:28 ` Peter Collingbourne
2020-04-29 10:27 ` Kevin Brodsky
2020-04-29 15:24 ` Catalin Marinas
2020-04-29 16:46 ` Dave Martin
2020-04-30 10:21 ` Catalin Marinas
2020-05-04 16:40 ` Dave Martin
2020-05-05 18:03 ` Luis Machado
2020-05-12 19:05 ` Luis Machado
2020-05-13 10:48 ` Catalin Marinas
2020-05-13 12:52 ` Luis Machado
2020-05-13 14:11 ` Catalin Marinas
2020-05-13 15:09 ` Luis Machado
2020-05-13 16:45 ` Luis Machado
2020-05-13 17:11 ` Catalin Marinas
2020-05-18 16:47 ` Dave Martin
2020-05-18 17:12 ` Luis Machado
2020-05-19 16:10 ` Catalin Marinas
2020-04-21 14:26 ` [PATCH v3 20/23] fs: Allow copy_mount_options() to access user-space in a single pass Catalin Marinas
2020-04-21 15:29 ` Al Viro
2020-04-21 16:45 ` Catalin Marinas
2020-04-27 16:56 ` Dave Martin
2020-04-28 14:06 ` Catalin Marinas
2020-04-29 10:28 ` Dave Martin
2020-04-28 18:16 ` Kevin Brodsky
2020-04-28 19:40 ` Catalin Marinas
2020-04-29 11:58 ` Catalin Marinas
2020-04-28 19:36 ` Catalin Marinas
2020-04-29 10:26 ` Dave Martin
2020-04-29 13:52 ` Catalin Marinas
2020-05-04 16:40 ` Dave Martin
2020-04-21 14:26 ` [PATCH v3 21/23] arm64: mte: Check the DT memory nodes for MTE support Catalin Marinas
2020-04-24 13:57 ` Catalin Marinas
2020-04-24 16:17 ` Catalin Marinas
2020-04-27 11:14 ` Suzuki K Poulose [this message]
2020-04-21 14:26 ` [PATCH v3 22/23] arm64: mte: Kconfig entry Catalin Marinas
2020-04-21 14:26 ` [PATCH v3 23/23] arm64: mte: Add Memory Tagging Extension documentation Catalin Marinas
2020-04-29 16:47 ` Dave Martin
2020-04-30 16:23 ` Catalin Marinas
2020-05-04 16:46 ` Dave Martin
2020-05-11 16:40 ` Catalin Marinas
2020-05-13 15:48 ` Dave Martin
2020-05-14 11:37 ` Catalin Marinas
2020-05-15 10:38 ` Catalin Marinas
2020-05-15 11:14 ` Szabolcs Nagy
2020-05-15 11:27 ` Catalin Marinas
2020-05-15 12:04 ` Szabolcs Nagy
2020-05-15 12:13 ` Catalin Marinas
2020-05-15 12:53 ` Szabolcs Nagy
2020-05-18 16:52 ` Dave Martin
2020-05-18 17:13 ` Catalin Marinas
2020-05-05 10:32 ` Szabolcs Nagy
2020-05-05 17:30 ` Catalin Marinas
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