From: Takahiro Kuwano <tkuw584924@gmail.com>
To: Tudor.Ambarus@microchip.com, p.yadav@ti.com, michael@walle.cc
Cc: miquel.raynal@bootlin.com, richard@nod.at,
Bacem.Daassi@infineon.com, Takahiro.Kuwano@infineon.com,
linux-mtd@lists.infradead.org
Subject: Re: [PATCH v14 8/8] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups
Date: Wed, 4 May 2022 16:59:48 +0900 [thread overview]
Message-ID: <0d2d0001-78f8-32d1-78eb-0559f8865363@gmail.com> (raw)
In-Reply-To: <39161526-fc95-63fc-8b43-83c2e539ae36@microchip.com>
On 5/4/2022 4:47 PM, Tudor.Ambarus@microchip.com wrote:
> On 5/4/22 10:38, Takahiro Kuwano wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi Tudor,
>
> Hi!
>
>>
>> On 5/3/2022 5:16 PM, Tudor Ambarus wrote:
>>> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>>
>>> The S25HL-T/S25HS-T family is the Infineon SEMPER Flash with Quad SPI.
>>>
>>> These Infineon chips support volatile version of configuration registers
>>> and it is recommended to update volatile registers in the field application
>>> due to a risk of the non-volatile registers corruption by power interrupt.
>>> Add support for volatile QE bit.
>>>
>>> For the single-die package parts (512Mb and 1Gb), only bottom 4KB and
>>> uniform sector sizes are supported. This is due to missing or incorrect
>>> entries in SMPT. Fixup for other sector sizes configurations will be
>>> followed up as needed.
>>>
>>> Tested on Xilinx Zynq-7000 FPGA board.
>>>
>>> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
>>> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>>> ---
>>> drivers/mtd/spi-nor/spansion.c | 125 +++++++++++++++++++++++++++++++++
>>> 1 file changed, 125 insertions(+)
>>>
>>> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
>>> index e130f5398763..f78a15b985ea 100644
>>> --- a/drivers/mtd/spi-nor/spansion.c
>>> +++ b/drivers/mtd/spi-nor/spansion.c
>>> @@ -14,6 +14,8 @@
>>> #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
>>> #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
>>> #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
>>> +#define SPINOR_REG_CYPRESS_CFR1V 0x00800002
>>> +#define SPINOR_REG_CYPRESS_CFR1V_QUAD_EN BIT(1) /* Quad Enable */
>>> #define SPINOR_REG_CYPRESS_CFR2V 0x00800003
>>> #define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb
>>> #define SPINOR_REG_CYPRESS_CFR3V 0x00800004
>>> @@ -113,6 +115,63 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
>>> return 0;
>>> }
>>>
>>> +/**
>>> + * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
>>> + * register.
>>> + * @nor: pointer to a 'struct spi_nor'
>>> + *
>>> + * It is recommended to update volatile registers in the field application due
>>> + * to a risk of the non-volatile registers corruption by power interrupt. This
>>> + * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
>>> + * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
>>> + * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
>>> + * also set during Flash power-up.
>>> + *
>>> + * Return: 0 on success, -errno otherwise.
>>> + */
>>> +static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
>>> +{
>>> + struct spi_mem_op op;
>>> + u8 cfr1v_written;
>>> + int ret;
>>> +
>>> + op = (struct spi_mem_op)
>>> + CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_nbytes,
>>> + SPINOR_REG_CYPRESS_CFR1V,
>>> + nor->bouncebuf);
>>> +
>> The following lines are missing.
>>
>> ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
>> if (ret)
>> return ret;
>
> Sorry, I'll add them in the next version, seems that I handled the conflicts
> badly :). Does it work with the read? Have you tested the patch set?
>
No problem. Yes, I tested and it's working.
Thanks again,
Takahiro
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next prev parent reply other threads:[~2022-05-04 8:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 8:16 [PATCH v14 0/8] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 1/8] mtd: spi-nor: s/addr_width/addr_nbytes Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 2/8] mtd: spi-nor: core: Shrink the storage size of the flash_info's addr_nbytes Tudor Ambarus
2022-05-03 8:27 ` Tudor.Ambarus
2022-05-03 8:35 ` Tudor.Ambarus
2022-05-03 8:16 ` [PATCH v14 3/8] mtd: spi-nor: sfdp: Clarify that nor->read_{opcode, dummy} are uninitialized Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 4/8] mtd: spi-nor: Do not change nor->addr_nbytes at SFDP parsing time Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 5/8] mtd: spi-nor: core: Couple the number of address bytes with the address mode Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 6/8] mtd: spi-nor: Retain nor->addr_width at 4BAIT parse Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 7/8] mtd: spi-nor: spansion: Add local function to discover page size Tudor Ambarus
2022-05-03 8:16 ` [PATCH v14 8/8] mtd: spi-nor: spansion: Add s25hl-t/s25hs-t IDs and fixups Tudor Ambarus
2022-05-04 7:38 ` Takahiro Kuwano
2022-05-04 7:47 ` Tudor.Ambarus
2022-05-04 7:59 ` Takahiro Kuwano [this message]
2022-05-04 7:56 ` [PATCH v14 0/8] mtd: spi-nor: Add support for Infineon s25hl-t/s25hs-t Takahiro Kuwano
2022-05-04 9:55 ` Tudor.Ambarus
2022-05-09 2:37 ` Takahiro Kuwano
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