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From: Han Xu <han.xu@nxp.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Bough Chen <haibo.chen@nxp.com>,
	"ashish.kumar@nxp.com" <ashish.kumar@nxp.com>,
	"yogeshgaur.83@gmail.com" <yogeshgaur.83@gmail.com>,
	"broonie@kernel.org" <broonie@kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org"
	<krzysztof.kozlowski+dt@linaro.org>,
	"singh.kuldeep87k@gmail.com" <singh.kuldeep87k@gmail.com>,
	"tudor.ambarus@microchip.com" <tudor.ambarus@microchip.com>,
	"p.yadav@ti.com" <p.yadav@ti.com>,
	"michael@walle.cc" <michael@walle.cc>,
	"miquel.raynal@bootlin.com" <miquel.raynal@bootlin.com>,
	"richard@nod.at" <richard@nod.at>,
	"vigneshr@ti.com" <vigneshr@ti.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"festevam@gmail.com" <festevam@gmail.com>,
	dl-linux-imx <linux-imx@nxp.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"zhengxunli@mxic.com.tw" <zhengxunli@mxic.com.tw>
Subject: Re: [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly
Date: Tue, 5 Jul 2022 09:31:00 -0500	[thread overview]
Message-ID: <20220705143100.kkyjzllastptaoqe@umbrella> (raw)
In-Reply-To: <777026d0-578c-500f-7da4-0e81fc211df2@linaro.org>

On 22/07/05 04:03PM, Krzysztof Kozlowski wrote:
> On 05/07/2022 16:00, Han Xu wrote:
> >> So we probably misunderstood each other... looking at the driver it also explains
> >> the confusing. You encoded here register value which is pretty often wrong
> >> approach.
> >>
> >> This should be instead meaningful value for the user of the bindings, so usually
> >> using one of property units:
> >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2F&amp;data=05%7C01%7Chan.xu%40nxp.com%7C8b8e3e6291c24579020308da5e8f2916%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637926266207468995%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=KHgjKLX7M8CYfJoWqpVhNdZc%2FlZhZxp6CuaPTUYgwE8%3D&amp;reserved=0
> >> %2Fdevicetree-org%2Fdt-
> >> schema%2Fblob%2Fmain%2Fdtschema%2Fschemas%2Fproperty-
> >> units.yaml&amp;data=05%7C01%7Chan.xu%40nxp.com%7C0ffe3d706e064f14382
> >> 108da5e8a5add%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6379262
> >> 45564450475%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV
> >> 2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=Q4
> >> SfVnBN%2BQ0vYKJzRf%2FXZkCA1WGyPV9doFcb%2BLSKx4w%3D&amp;reserved=0
> >>
> >> I think you could use here clock cycles or clock phase, but then it has to be obvious
> >> it is that unit.
> > 
> > Hi Krzysztof, 
> > 
> > Let me clarify it, in the document a term "delay cell" was used to descript this register bit. 
> 
> Which document? The bindings (I cannot find it there)? Commit msg?

The SoC Reference Manual.

> 
> > Each delay cell equals "1/32 clock phase", so the unit of delay cell is clock phase. The value user need set in DT just number to define how many delay cells needed.
> 
> Your bindings did not say this at all.

I will explain all details in v2 patch.

> 
> Best regards,
> Krzysztof

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  reply	other threads:[~2022-07-05 14:31 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-05  9:11 [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi haibo.chen
2022-07-05  9:11 ` [PATCH 02/11] spi: spi-nxp-fspi: change the default lut index haibo.chen
2022-07-05  9:11 ` [PATCH 03/11] spi: spi-nxp-fspi: add DTR mode support haibo.chen
2022-07-05  9:11 ` [PATCH 04/11] spi: spi-nxp-fspi: add function to select sample clock source for flash reading haibo.chen
2022-07-06 21:02   ` Michael Walle
2022-07-05  9:11 ` [PATCH 05/11] spi: spi-nxp-fspi: Add quirk to disable DTR support haibo.chen
2022-07-05 13:50   ` Michael Walle
2022-07-05  9:11 ` [PATCH 06/11] spi: spi-nxp-fspi: enable octal ddr for iMX8QM/QXP/DXL haibo.chen
2022-07-05  9:11 ` [PATCH 07/11] dt-bindings: spi: spi-nxp-fspi: add a new property nxp,fspi-dll-slvdly haibo.chen
2022-07-05  9:48   ` Krzysztof Kozlowski
2022-07-05 10:28     ` Bough Chen
2022-07-05 10:36       ` Krzysztof Kozlowski
2022-07-05 13:19         ` Han Xu
2022-07-05 13:29           ` Krzysztof Kozlowski
2022-07-05 14:00             ` Han Xu
2022-07-05 14:03               ` Krzysztof Kozlowski
2022-07-05 14:31                 ` Han Xu [this message]
2022-07-05 14:06               ` Michael Walle
2022-07-05 14:12                 ` Krzysztof Kozlowski
2022-07-05 14:52                   ` Han Xu
2022-07-05 14:58                     ` Michael Walle
2022-07-05 15:07                       ` Mark Brown
2022-07-05 15:38                     ` Krzysztof Kozlowski
2022-07-05 15:50                       ` Han Xu
2022-07-06 16:11                         ` Rob Herring
2022-07-06 20:59                           ` Michael Walle
2022-07-05  9:11 ` [PATCH 08/11] mtd: spi-nor: macronix: add support for Macronix octaflash haibo.chen
2022-07-05  9:11 ` [PATCH 09/11] mtd: spi-nor: macronix: add mx25uw51345g OPI mode support haibo.chen
2022-07-18  6:57   ` Michael Walle
2022-07-05  9:11 ` [PATCH 10/11] arm64: dts: imx8ulp: add flexspi support haibo.chen
2022-07-05  9:11 ` [PATCH 11/11] arm64: dts: imx8qm/imx8qxp: " haibo.chen
2022-07-05 14:01 ` [PATCH 01/11] spi: spi-nxp-fspi: enable runtime pm for fspi Michael Walle
2022-07-05 23:06   ` Han Xu

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