From: Vignesh Raghavendra <vigneshr@ti.com>
To: Michael Walle <michael@walle.cc>
Cc: js07.lee@gmail.com, linux-mtd@lists.infradead.org,
tudor.ambarus@microchip.com, Jungseung Lee <js07.lee@samsung.com>
Subject: Re: [SPAM] Re: [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support
Date: Mon, 3 Feb 2020 23:01:56 +0530 [thread overview]
Message-ID: <62b66868-5a18-4fc4-f18e-6b4c39fdb65d@ti.com> (raw)
In-Reply-To: <9966c63930b47103e78873fb82dc16f2@walle.cc>
Hi,
On 2/3/2020 8:08 PM, Michael Walle wrote:
> Am 2020-02-03 14:56, schrieb Vignesh Raghavendra:
[...]
>>
>> Flash devices have variable sector size, 64KB, 128KB or 256KB... While
>> mapping of number of sectors locked to BP bits is dependent on rules 1
>> to 3 you mentioned below, the size or area of flash protected depends on
>> sector size.
>
> Is there any flash device which has another sector size != 64KiB for the
> BP bits?
I cannot seem to find BP scheme for Micron mt35x series but they all
have 128KB sectors with 4 bit block protection scheme:
https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt35x_xccela/die-rev-a/xccela_flash_memory_data_sheet_brief.pdf
Another example would be s25fl512s with 256KB sector with 3 bit BP:
https://www.cypress.com/file/177971/download
>
>> So, the current formula in spi-nor.c (ignoring TB and other boilerplate):
>>
>> pow = ilog2(mtd->size) - ilog2(lock_len);
>> val = mask - (pow << shift);
>>
>> This works only for devices with 64KB sector size as 8MB flash with 64KB
>> sector size would have 128 sectors (BP0-2 => 0b111 => 2^7).
>
> It also only works with flashes >= 4MiB. See fix below. And IMHO this is
> exactly
> the same "problem" the flashes with 4 BP bits have.
>
Yes agree, but that patch is assumes sector size to be 64KB and
once generalized would mostly be equivalent to below formula.
>> A more generic formula would be:
>>
>> Find n where 2^(n - 1) = len/sector-size
>> OR 2^ (n - 1) = len * n_sectors / mtd->size
>>
>> Which solves to:
>>
>> pow = ilog2(mtd->size) - ilog2(lock_len);
>> val = ilog2(nor->n_sectors) + 1 - pow;
>>
>> I see this is what Jungseung has tried to implement here. Please
>> correct me if I got this wrong.
>>
>> This, combined with point (3) below should provide a generic
>> implementation that should support a wide variety of flashes.
>>
>> Of course, there are always exceptions and they need to be handled using
>> custom hooks.
>>
>> I don't have the patch that you shared with Jungseung. I would greatly
>> appreciate, if you and Jungseung could work on patch with above logic as
>> well as fixes to handle overflow case?
>
> https://lore.kernel.org/linux-mtd/20200123170130.8289-1-michael@walle.cc/
>
> As I said, that should work for both 3 and 4 bits. But be aware that this
> is an RFC and I've just tested it in in userspace, like the calculation
> of the bits and transferred that into the driver. So one would actually
> have to test that. But apparently no one had a even applied it.
>
Sorry, I haven't looked at that patch. But I think better alternative would
be extend this patch to support overflow case.
Would it be possible to test this patch on flashes <32MBit, if you have
access to?
Regards
Vignesh
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next prev parent reply other threads:[~2020-02-03 17:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200113055910epcas1p4f97dfeb465b00d66649d6321cffc7b5a@epcas1p4.samsung.com>
2020-01-13 5:59 ` [PATCH v3 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Jungseung Lee
[not found] ` <CGME20200113055910epcas1p377b2618bea2ca860acac2b6f34e2b83e@epcas1p3.samsung.com>
2020-01-13 5:59 ` [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support Jungseung Lee
2020-01-14 10:49 ` Tudor.Ambarus
2020-01-17 15:06 ` Jungseung Lee
2020-01-22 11:42 ` Jungseung Lee
2020-01-22 14:31 ` Tudor.Ambarus
2020-01-22 17:14 ` Michael Walle
2020-01-23 3:59 ` Jungseung Lee
2020-01-23 8:15 ` Michael Walle
2020-02-11 7:52 ` chenxiang (M)
2020-03-04 5:20 ` Jungseung Lee
2020-03-04 8:36 ` chenxiang (M)
2020-03-07 7:40 ` Jungseung Lee
2020-01-22 19:36 ` Michael Walle
2020-01-23 6:22 ` Jungseung Lee
2020-01-23 8:10 ` Michael Walle
2020-01-23 8:53 ` Jungseung Lee
2020-01-23 9:31 ` Michael Walle
2020-01-28 11:01 ` Jungseung Lee
2020-01-28 12:29 ` [SPAM] " Michael Walle
2020-01-30 8:17 ` Jungseung Lee
2020-01-30 8:36 ` [SPAM] " Michael Walle
2020-01-30 10:07 ` Jungseung Lee
2020-02-03 13:56 ` Vignesh Raghavendra
2020-02-03 14:38 ` [SPAM] " Michael Walle
2020-02-03 14:58 ` Jungseung Lee
2020-02-03 17:31 ` Vignesh Raghavendra [this message]
2020-02-07 12:17 ` Tudor.Ambarus
2020-02-10 8:33 ` Michael Walle
2020-02-10 9:47 ` Tudor.Ambarus
2020-02-10 9:59 ` Tudor.Ambarus
2020-02-10 10:40 ` Michael Walle
2020-02-10 11:27 ` Tudor.Ambarus
2020-02-10 12:14 ` Michael Walle
2020-02-10 15:50 ` Tudor.Ambarus
2020-02-10 10:29 ` Michael Walle
2020-02-10 11:26 ` Tudor.Ambarus
2020-02-19 10:50 ` Jungseung Lee
2020-02-19 11:08 ` Michael Walle
2020-02-19 11:23 ` Jungseung Lee
2020-02-19 11:36 ` Michael Walle
2020-02-20 19:09 ` Michael Walle
2020-02-21 9:30 ` Tudor.Ambarus
2020-02-25 8:20 ` Tudor.Ambarus
2020-02-25 9:25 ` Jungseung Lee
[not found] ` <CGME20200113055910epcas1p384c04182e7c643163d659d42fafd01b3@epcas1p3.samsung.com>
2020-01-13 5:59 ` [PATCH v3 3/3] mtd: spi-nor: support lock/unlock for a few Micron chips Jungseung Lee
2020-01-13 12:30 ` John Garry
2020-01-13 12:40 ` Jungseung Lee
2020-01-13 12:45 ` Jungseung Lee
2020-01-13 13:00 ` John Garry
2020-02-17 0:18 ` [PATCH v3 1/3] mtd: spi-nor: introduce SR_BP_SHIFT define Tudor.Ambarus
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