From: Greg Ungerer <gerg@kernel.org>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: s.hauer@pengutronix.de, Boris Brezillon <bbrezillon@kernel.org>,
linux-mtd@lists.infradead.org,
Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
Miquel Raynal <miquel.raynal@bootlin.com>
Subject: Re: GPMI iMX6ull timeout on DMA
Date: Fri, 2 Aug 2019 17:19:14 +1000 [thread overview]
Message-ID: <6a3598ae-0753-e95d-d6a4-b11eb335db9c@kernel.org> (raw)
In-Reply-To: <20190731082823.6284f5a9@collabora.com>
Hi Boris,
On 31/7/19 4:28 pm, Boris Brezillon wrote:
> On Wed, 31 Jul 2019 12:05:44 +1000
> Greg Ungerer <gerg@kernel.org> wrote:
>
>> Hi Miquel, Boris,
>>
>> On 30/7/19 6:38 pm, Miquel Raynal wrote:
>>> Greg Ungerer <gerg@kernel.org> wrote on Tue, 30 Jul 2019 16:06:55 +1000:
>>>> On 30/7/19 10:41 am, Greg Ungerer wrote:
>>>>> On 30/7/19 10:28 am, Greg Ungerer wrote:
>>>>>> On 29/7/19 10:47 pm, Miquel Raynal wrote:
>>>>>>> Greg Ungerer <gerg@kernel.org> wrote on Mon, 29 Jul 2019 22:33:56 +1000:
>>>>>>>> On 29/7/19 6:36 pm, Miquel Raynal wrote:
>>>>>>>>> Greg Ungerer <gerg@kernel.org> wrote on Mon, 29 Jul 2019 16:41:51 +1000:
>>>>> [snip]
>>>> Not sure if this is a useful data point... But I modified that
>>>> nand_init_data_interface() loop to start checking from data mode 4.
>>>> So now on every boot it defaults to mode 4. That has been running
>>>> most of the day, up to 900 boot cycles now, no failures.
>>>
>>> Ok so after having chatted quite a bit with Boris, it is very likely
>>> that, for these chips, the timings in mode 5 are too tight. It could
>>> fail the GET_FEATURES once in mode 5. Can you please dump every single
>>> intermediate value in gpmi_nfc_compute_timings() (period, *_cycles,
>>> use of half pêriods, tRP, sample delay, etc) as well as the content
>>> of /sys/kernel/debug/clk/clk_summary (you'll need debugfs support
>>> enabled and mounted).
>>>
>>> Also, can you be sure that the NAND chip is powered with 3.3V?
>>
>> Yes, 3.3V NAND chip.
>>
>> Using the attached patch I get the following trace:
>>
>> ...
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(426): gpmi_nfc_compute_timings()
>> sdr->tBERS_max=65535000000
>> sdr->tCCS_min=500000000
>> sdr->tPROG_max=65535000000
>> sdr->tR_max=200000000000000
>> sdr->tALH_min=20000
>> sdr->tADL_min=400000
>> sdr->tALS_min=50000
>> sdr->tAR_min=25000
>> sdr->tCEA_max=100000
>> sdr->tCEH_min=20000
>> sdr->tCH_min=20000
>> sdr->tCHZ_max=100000
>> sdr->tCLH_min=20000
>> sdr->tCLR_min=20000
>> sdr->tCLS_min=50000
>> sdr->tCOH_min=0
>> sdr->tCS_min=70000
>> sdr->tDH_min=20000
>> sdr->tDS_min=40000
>> sdr->tFEAT_max=1000000
>> sdr->tIR_min=10000
>> sdr->tITC_max=1000000
>> sdr->tRC_min=100000
>> sdr->tREA_max=40000
>> sdr->tREH_min=30000
>> sdr->tRHOH_min=0
>> sdr->tRHW_min=200000
>> sdr->tRHZ_max=200000
>> sdr->tRLOH_min=0
>> sdr->tRP_min=50000
>> sdr->tRR_min=40000
>> sdr->tRST_max=250000000000
>> sdr->tWB_max=200000
>> sdr->tWC_min=100000
>> sdr->tWH_min=30000
>> sdr->tWHR_min=120000
>> sdr->tWP_min=50000
>> sdr->tWW_min=100000
>> hw->clk_rate=22000000
>> wrn_dly_sel=0
>> period_ps=45454
>> addr_setup_cycles=2
>> data_setup_cycles=1
>> data_hold_cycles=1
>> busy_timeout_cycles=31302
>> hw->timing0=0x00020101
>> hw->timing1=0x60000000
>> dll_threshold_ps=12000
>> use_half_period=1
>> reference_period_ps=22727
>> tRP_ps=45454
>> sample_delay_ps=4294955664
>> sample_delay_factor=0
>> hw->ctrl1n=0x00000000
>> hw->ctrl1n=0x00000000
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(547): gpmi_nfc_apply_timings()
>> hw>clk_rate=22000000
>> clk_set_rate(r->clock[0], hw->clk_rate)=0
>> clk_get_rate(r->clock[0])=22000000
>> random: fast init done
>> nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
>> nand: Micron MT29F2G08ABAEAWP
>> nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(426): gpmi_nfc_compute_timings()
>> sdr->tBERS_max=3000000000
>> sdr->tCCS_min=100000
>> sdr->tPROG_max=600000000
>> sdr->tR_max=25000000
>> sdr->tALH_min=20000
>> sdr->tADL_min=400000
>> sdr->tALS_min=50000
>> sdr->tAR_min=25000
>> sdr->tCEA_max=100000
>> sdr->tCEH_min=20000
>> sdr->tCH_min=20000
>> sdr->tCHZ_max=100000
>> sdr->tCLH_min=20000
>> sdr->tCLR_min=20000
>> sdr->tCLS_min=50000
>> sdr->tCOH_min=0
>> sdr->tCS_min=70000
>> sdr->tDH_min=20000
>> sdr->tDS_min=40000
>> sdr->tFEAT_max=1000000
>> sdr->tIR_min=10000
>> sdr->tITC_max=1000000
>> sdr->tRC_min=100000
>> sdr->tREA_max=40000
>> sdr->tREH_min=30000
>> sdr->tRHOH_min=0
>> sdr->tRHW_min=200000
>> sdr->tRHZ_max=200000
>> sdr->tRLOH_min=0
>> sdr->tRP_min=50000
>> sdr->tRR_min=40000
>> sdr->tRST_max=250000000000
>> sdr->tWB_max=200000
>> sdr->tWC_min=100000
>> sdr->tWH_min=30000
>> sdr->tWHR_min=120000
>> sdr->tWP_min=50000
>> sdr->tWW_min=100000
>> hw->clk_rate=22000000
>> wrn_dly_sel=0
>> period_ps=45454
>> addr_setup_cycles=2
>> data_setup_cycles=1
>> data_hold_cycles=1
>> busy_timeout_cycles=555
>> hw->timing0=0x00020101
>> hw->timing1=0xb0000000
>> dll_threshold_ps=12000
>> use_half_period=1
>> reference_period_ps=22727
>> tRP_ps=45454
>> sample_delay_ps=4294955664
>> sample_delay_factor=0
>> hw->ctrl1n=0x00000000
>> hw->ctrl1n=0x00000000
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(547): gpmi_nfc_apply_timings()
>> hw>clk_rate=22000000
>> clk_set_rate(r->clock[0], hw->clk_rate)=0
>> clk_get_rate(r->clock[0])=22000000
>> gpmi-nand 1806000.gpmi-nand: use legacy bch geometry
>> drivers/mtd/nand/raw/nand_base.c(913): checking mode=5
>> drivers/mtd/nand/raw/nand_base.c(927): BREAKING AT mode=5
>> drivers/mtd/nand/raw/nand_base.c(932): chip->onfi_timing_mode_default=5
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(426): gpmi_nfc_compute_timings()
>> sdr->tBERS_max=3000000000
>> sdr->tCCS_min=100000
>> sdr->tPROG_max=600000000
>> sdr->tR_max=25000000
>> sdr->tALH_min=5000
>> sdr->tADL_min=400000
>> sdr->tALS_min=10000
>> sdr->tAR_min=10000
>> sdr->tCEA_max=25000
>> sdr->tCEH_min=20000
>> sdr->tCH_min=5000
>> sdr->tCHZ_max=30000
>> sdr->tCLH_min=5000
>> sdr->tCLR_min=10000
>> sdr->tCLS_min=10000
>> sdr->tCOH_min=15000
>> sdr->tCS_min=15000
>> sdr->tDH_min=5000
>> sdr->tDS_min=7000
>> sdr->tFEAT_max=1000000
>> sdr->tIR_min=0
>> sdr->tITC_max=1000000
>> sdr->tRC_min=20000
>> sdr->tREA_max=16000
>> sdr->tREH_min=7000
>> sdr->tRHOH_min=15000
>> sdr->tRHW_min=100000
>> sdr->tRHZ_max=100000
>> sdr->tRLOH_min=5000
>> sdr->tRP_min=10000
>> sdr->tRR_min=20000
>> sdr->tRST_max=500000000
>> sdr->tWB_max=100000
>> sdr->tWC_min=20000
>> sdr->tWH_min=7000
>> sdr->tWHR_min=80000
>> sdr->tWP_min=10000
>> sdr->tWW_min=100000
>> hw->clk_rate=100000000
>> wrn_dly_sel=3
>> period_ps=10000
>> addr_setup_cycles=1
>> data_setup_cycles=1
>> data_hold_cycles=1
>> busy_timeout_cycles=2510
>> hw->timing0=0x00010101
>> hw->timing1=0xe0000000
>> dll_threshold_ps=12000
>> use_half_period=0
>> reference_period_ps=10000
>> tRP_ps=10000
>> sample_delay_ps=80000
>> sample_delay_factor=8
>> hw->ctrl1n=0x00c00000
>> hw->ctrl1n=0x00c28000
>> drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c(547): gpmi_nfc_apply_timings()
>> hw>clk_rate=100000000
>> clk_set_rate(r->clock[0], hw->clk_rate)=0
>> clk_get_rate(r->clock[0])=99000000
>> Scanning device for bad blocks
>> 5 fixed-partitions partitions found on MTD device gpmi-nand
>> Creating 5 MTD partitions on "gpmi-nand":
>> 0x000000000000-0x000000500000 : "u-boot"
>> 0x000000500000-0x000000600000 : "u-boot-env"
>> 0x000000600000-0x000000800000 : "log"
>> 0x000000800000-0x000010000000 : "flash"
>> 0x000000000000-0x000010000000 : "all"
>> gpmi-nand 1806000.gpmi-nand: driver registered.
>> ...
>>
>>
>> And "cat /sys/kernel/debug/clk/clk_summary" gives:
>>
>> enable prepare protect duty
>> clock count count count rate accuracy phase cycle
>> ---------------------------------------------------------------------------------------------
>> dummy 2 2 0 0 0 0 50000
>> cko2_sel 0 0 0 0 0 0 50000
>> cko2_podf 0 0 0 0 0 0 50000
>> cko2 0 0 0 0 0 0 50000
>> cko1_sel 0 0 0 0 0 0 50000
>> cko1_podf 0 0 0 0 0 0 50000
>> cko1 0 0 0 0 0 0 50000
>> cko 0 0 0 0 0 0 50000
>> usbphy2_gate 1 1 0 0 0 0 50000
>> usbphy1_gate 1 1 0 0 0 0 50000
>> ipp_di1 0 0 0 0 0 0 50000
>> ipp_di0 0 0 0 0 0 0 50000
>> osc 6 6 0 24000000 0 0 50000
>> perclk_sel 1 1 0 24000000 0 0 50000
>> perclk 3 3 0 24000000 0 0 50000
>> pwm7 0 0 0 24000000 0 0 50000
>> pwm6 0 0 0 24000000 0 0 50000
>> pwm5 0 0 0 24000000 0 0 50000
>> i2c4 0 0 0 24000000 0 0 50000
>> pwm8 0 0 0 24000000 0 0 50000
>> pwm4 0 0 0 24000000 0 0 50000
>> pwm3 0 0 0 24000000 0 0 50000
>> pwm2 0 0 0 24000000 0 0 50000
>> pwm1 0 0 0 24000000 0 0 50000
>> i2c3 0 0 0 24000000 0 0 50000
>> i2c2 1 1 0 24000000 0 0 50000
>> i2c1 0 0 0 24000000 0 0 50000
>> gpt1_serial 1 1 0 24000000 0 0 50000
>> gpt1_bus 1 1 0 24000000 0 0 50000
>> epit2 0 0 0 24000000 0 0 50000
>> epit1 0 0 0 24000000 0 0 50000
>> gpt2_serial 0 0 0 24000000 0 0 50000
>> gpt2_bus 0 0 0 24000000 0 0 50000
>> periph_clk2_sel 0 0 0 24000000 0 0 50000
>> periph_clk2 0 0 0 24000000 0 0 50000
>> gpt_3m 0 0 0 3000000 0 0 50000
>> csi_sel 0 0 0 24000000 0 0 50000
>> csi_podf 0 0 0 24000000 0 0 50000
>> csi 0 0 0 24000000 0 0 50000
>> pll7 1 1 0 480000000 0 0 50000
>> pll7_bypass 1 1 0 480000000 0 0 50000
>> pll7_usb_host 1 1 0 480000000 0 0 50000
>> usbphy2 1 1 0 480000000 0 0 50000
>> pll6 1 1 0 500000000 0 0 50000
>> pll6_bypass 1 1 0 500000000 0 0 50000
>> pll6_enet 2 2 0 500000000 0 0 50000
>> enet_ptp_ref 1 1 0 25000000 0 0 50000
>> enet_ptp 1 1 0 25000000 0 0 50000
>> enet2_ref 0 0 0 50000000 0 0 50000
>> enet_ref_125m 0 0 0 50000000 0 0 50000
>> enet_ref 2 2 0 50000000 0 0 50000
>> pll5 0 0 0 296600000 0 0 50000
>> pll5_bypass 0 0 0 296600000 0 0 50000
>> pll5_video 0 0 0 296600000 0 0 50000
>> pll5_post_div 0 0 0 74150000 0 0 50000
>> pll5_video_div 0 0 0 74150000 0 0 50000
>> pll4 0 0 0 147456000 0 0 50000
>> pll4_bypass 0 0 0 147456000 0 0 50000
>> pll4_audio 0 0 0 147456000 0 0 50000
>> pll4_post_div 0 0 0 36864000 0 0 50000
>> pll4_audio_div 0 0 0 36864000 0 0 50000
>> pll3 1 1 0 480000000 0 0 50000
>> pll3_bypass 1 1 0 480000000 0 0 50000
>> pll3_usb_otg 2 2 0 480000000 0 0 50000
>> spdif_sel 0 0 0 480000000 0 0 50000
>> spdif_pred 0 0 0 240000000 0 0 50000
>> spdif_podf 0 0 0 30000000 0 0 50000
>> spdif 0 0 0 30000000 0 0 50000
>> esai_sel 0 0 0 480000000 0 0 50000
>> esai_pred 0 0 0 240000000 0 0 50000
>> esai_podf 0 0 0 30000000 0 0 50000
>> esai_extal 0 0 0 30000000 0 0 50000
>> qspi1_sel 0 0 0 480000000 0 0 50000
>> qspi1_podf 0 0 0 240000000 0 0 50000
>> qspi1 0 0 0 240000000 0 0 50000
>> ldb_di1_div_7 0 0 0 68571428 0 0 50000
>> ldb_di1 0 0 0 68571428 0 0 50000
>> ldb_di1_div_3_5 0 0 0 137142857 0 0 50000
>> periph2_clk2_sel 0 0 0 480000000 0 0 50000
>> periph2_clk2 0 0 0 480000000 0 0 50000
>> pll3_60m 0 0 0 60000000 0 0 50000
>> can_sel 0 0 0 60000000 0 0 50000
>> can_podf 0 0 0 30000000 0 0 50000
>> can2_serial 0 0 0 30000000 0 0 50000
>> can1_serial 0 0 0 30000000 0 0 50000
>> ecspi_sel 0 0 0 60000000 0 0 50000
>> ecspi_podf 0 0 0 60000000 0 0 50000
>> ecspi4 0 0 0 60000000 0 0 50000
>> ecspi3 0 0 0 60000000 0 0 50000
>> ecspi2 0 0 0 60000000 0 0 50000
>> ecspi1 0 0 0 60000000 0 0 50000
>> pll3_80m 1 1 0 80000000 0 0 50000
>> uart_sel 1 1 0 80000000 0 0 50000
>> uart_podf 1 1 0 80000000 0 0 50000
>> uart8_serial 0 0 0 80000000 0 0 50000
>> uart7_serial 0 0 0 80000000 0 0 50000
>> uart1_serial 1 2 0 80000000 0 0 50000
>> uart6_serial 0 0 0 80000000 0 0 50000
>> uart5_serial 0 0 0 80000000 0 0 50000
>> uart4_serial 0 0 0 80000000 0 0 50000
>> uart3_serial 0 0 0 80000000 0 0 50000
>> uart2_serial 0 0 0 80000000 0 0 50000
>> pll3_pfd3_454m 0 0 0 454736842 0 0 50000
>> pll3_pfd2_508m 0 0 0 508235294 0 0 50000
>> epdc_pre_sel 0 0 0 508235294 0 0 50000
>> epdc_podf 0 0 0 254117647 0 0 50000
>> epdc_pix 0 0 0 254117647 0 0 50000
>> epdc_sel 0 0 0 254117647 0 0 50000
>> sai1_sel 0 0 0 508235294 0 0 50000
>> sai1_pred 0 0 0 127058824 0 0 50000
>> sai1_podf 0 0 0 63529412 0 0 50000
>> sai1 0 0 0 63529412 0 0 50000
>> sai2_sel 0 0 0 508235294 0 0 50000
>> sai2_pred 0 0 0 127058824 0 0 50000
>> sai2_podf 0 0 0 63529412 0 0 50000
>> sai2 0 0 0 63529412 0 0 50000
>> sai3_sel 0 0 0 508235294 0 0 50000
>> sai3_pred 0 0 0 127058824 0 0 50000
>> sai3_podf 0 0 0 63529412 0 0 50000
>> sai3 0 0 0 63529412 0 0 50000
>> pll3_pfd1_540m 0 0 0 540000000 0 0 50000
>> lcdif_pre_sel 0 0 0 540000000 0 0 50000
>> lcdif_pred 0 0 0 270000000 0 0 50000
>> lcdif_podf 0 0 0 135000000 0 0 50000
>> lcdif_pix 0 0 0 135000000 0 0 50000
>> iomuxc 0 0 0 135000000 0 0 50000
>> lcdif_sel 0 0 0 135000000 0 0 50000
>> pll3_pfd0_720m 0 0 0 720000000 0 0 50000
>> usbphy1 1 1 0 480000000 0 0 50000
>> pll2 1 1 0 528000000 0 0 50000
>> pll2_bypass 1 1 0 528000000 0 0 50000
>> pll2_bus 2 2 0 528000000 0 0 50000
>> ca7_secondary_sel 0 0 0 528000000 0 0 50000
>> step 0 0 0 528000000 0 0 50000
>> periph_pre 1 1 0 528000000 0 0 50000
>> periph 3 3 0 528000000 0 0 50000
>> ahb 7 7 0 132000000 0 0 50000
>> sdma 0 0 0 132000000 0 0 50000
>> rom 1 1 0 132000000 0 0 50000
>> esai_mem 0 0 0 132000000 0 0 50000
>> esai_ipg 0 0 0 132000000 0 0 50000
>> aips_tz3 1 1 0 132000000 0 0 50000
>> enet_ahb 2 2 0 132000000 0 0 50000
>> dcp 0 0 0 132000000 0 0 50000
>> asrc_mem 0 0 0 132000000 0 0 50000
>> asrc_ipg 0 0 0 132000000 0 0 50000
>> aips_tz2 1 1 0 132000000 0 0 50000
>> aips_tz1 1 1 0 132000000 0 0 50000
>> ipg 10 10 0 66000000 0 0 50000
>> wdog3 0 0 0 66000000 0 0 50000
>> uart8_ipg 0 0 0 66000000 0 0 50000
>> usboh3 2 2 0 66000000 0 0 50000
>> sai2_ipg 0 0 0 66000000 0 0 50000
>> sai1_ipg 0 0 0 66000000 0 0 50000
>> uart7_ipg 0 0 0 66000000 0 0 50000
>> uart1_ipg 1 2 0 66000000 0 0 50000
>> sai3_ipg 0 0 0 66000000 0 0 50000
>> spdif_gclk 0 0 0 66000000 0 0 50000
>> spba 0 0 0 66000000 0 0 50000
>> wdog2 0 0 0 66000000 0 0 50000
>> kpp 0 0 0 66000000 0 0 50000
>> mmdc_p1_ipg 0 0 0 66000000 0 0 50000
>> mmdc_p0_ipg 2 2 0 66000000 0 0 50000
>> wdog1 1 1 0 66000000 0 0 50000
>> gpio4 1 1 0 66000000 0 0 50000
>> uart6_ipg 0 0 0 66000000 0 0 50000
>> uart5_ipg 0 0 0 66000000 0 0 50000
>> gpio3 1 1 0 66000000 0 0 50000
>> ocotp 0 0 0 66000000 0 0 50000
>> gpio5 1 1 0 66000000 0 0 50000
>> gpio1 1 1 0 66000000 0 0 50000
>> uart4_ipg 0 0 0 66000000 0 0 50000
>> adc1 0 0 0 66000000 0 0 50000
>> uart3_ipg 0 0 0 66000000 0 0 50000
>> adc2 0 0 0 66000000 0 0 50000
>> gpio2 1 1 0 66000000 0 0 50000
>> uart2_ipg 0 0 0 66000000 0 0 50000
>> can2_ipg 0 0 0 66000000 0 0 50000
>> can1_ipg 0 0 0 66000000 0 0 50000
>> enet 2 2 0 66000000 0 0 50000
>> axi_sel 1 1 0 528000000 0 0 50000
>> axi_podf 2 2 0 264000000 0 0 50000
>> axi 1 1 0 264000000 0 0 50000
>> eim_slow_sel 0 0 0 264000000 0 0 50000
>> eim_slow_podf 0 0 0 132000000 0 0 50000
>> eim 0 0 0 132000000 0 0 50000
>> lcdif_apb 0 0 0 264000000 0 0 50000
>> pxp 0 0 0 264000000 0 0 50000
>> epdc_aclk 0 0 0 264000000 0 0 50000
>> pll2_pfd3_594m 0 0 0 594000000 0 0 50000
>> ldb_di0_sel 0 0 0 594000000 0 0 50000
>> ldb_di0_div_7 0 0 0 84857142 0 0 50000
>> ldb_di0 0 0 0 84857142 0 0 50000
>> ldb_di0_div_3_5 0 0 0 169714285 0 0 50000
>> pll2_pfd2_396m 2 2 0 396000000 0 0 50000
>> enfc_sel 0 0 0 396000000 0 0 50000
>> enfc_pred 0 0 0 99000000 0 0 50000
>> enfc_podf 0 0 0 99000000 0 0 50000
>> gpmi_io 0 0 0 99000000 0 0 50000
>> usdhc1_sel 0 0 0 396000000 0 0 50000
>> usdhc1_podf 0 0 0 198000000 0 0 50000
>> usdhc1 0 0 0 198000000 0 0 50000
>> usdhc2_sel 0 0 0 396000000 0 0 50000
>> usdhc2_podf 0 0 0 198000000 0 0 50000
>> usdhc2 0 0 0 198000000 0 0 50000
>> bch_sel 1 1 0 396000000 0 0 50000
>> bch_podf 1 1 0 99000000 0 0 50000
>> gpmi_apb 0 0 0 99000000 0 0 50000
>> gpmi_bch_apb 0 0 0 99000000 0 0 50000
>> per_bch 0 0 0 99000000 0 0 50000
>> apbh_dma 1 1 0 99000000 0 0 50000
>> gpmi_sel 0 0 0 396000000 0 0 50000
>> gpmi_podf 0 0 0 99000000 0 0 50000
>> gpmi_bch 0 0 0 99000000 0 0 50000
>> periph2_pre 1 1 0 396000000 0 0 50000
>> periph2 2 2 0 396000000 0 0 50000
>> mmdc_podf 2 2 0 396000000 0 0 50000
>> mmdc_p0_fast 1 1 0 396000000 0 0 50000
>> axi_alt_sel 0 0 0 396000000 0 0 50000
>> pll2_198m 0 0 0 198000000 0 0 50000
>> pll2_pfd1_594m 0 0 0 594000000 0 0 50000
>> pll2_pfd0_352m 0 0 0 352000000 0 0 50000
>> pll1 1 1 0 900000000 0 0 50000
>> pll1_bypass 1 1 0 900000000 0 0 50000
>> pll1_sys 1 1 0 900000000 0 0 50000
>> pll1_sw 1 1 0 900000000 0 0 50000
>> arm 1 1 0 900000000 0 0 50000
>> pll7_bypass_src 0 0 0 24000000 0 0 50000
>> pll6_bypass_src 0 0 0 24000000 0 0 50000
>> pll5_bypass_src 0 0 0 24000000 0 0 50000
>> pll4_bypass_src 0 0 0 24000000 0 0 50000
>> pll3_bypass_src 0 0 0 24000000 0 0 50000
>> pll2_bypass_src 0 0 0 24000000 0 0 50000
>> pll1_bypass_src 0 0 0 24000000 0 0 50000
>> ckil 0 0 0 32768 0 0 50000
>>
>>
>> Note that this was generated on a normal boot up (not failure).
>
> The values looks good. Can you try with the below diff applied?
> --->8---
> diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> index 334fe3130285..9771f6a82abe 100644
> --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
> @@ -721,12 +721,10 @@ static void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
> writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
>
> /* Wait 64 clock cycles before using the GPMI after enabling the DLL */
> - dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64;
> - if (!dll_wait_time_us)
> - dll_wait_time_us = 1;
> + dll_wait_time_us = DIV_ROUND_UP(USEC_PER_SEC * 64, hw->clk_rate);
>
> /* Wait for the DLL to settle. */
> - udelay(dll_wait_time_us);
> + usleep_range(dll_wait_time_us, dll_wait_time_us * 10);
> }
>
> static int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
Running a boot test with this now. Has run for a couple of hours, but I
want to give it a really good run over the weekend. Will report results
on Monday.
Thanks
Greg
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next prev parent reply other threads:[~2019-08-02 7:19 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-29 6:41 GPMI iMX6ull timeout on DMA Greg Ungerer
2019-07-29 8:36 ` Miquel Raynal
2019-07-29 8:42 ` Michael Nazzareno Trimarchi
2019-07-29 12:18 ` Greg Ungerer
2019-07-29 12:20 ` Michael Nazzareno Trimarchi
2019-07-29 12:33 ` Greg Ungerer
2019-07-29 12:47 ` Miquel Raynal
2019-07-29 12:49 ` Michael Nazzareno Trimarchi
2019-07-29 12:55 ` Miquel Raynal
2019-07-29 13:00 ` Michael Nazzareno Trimarchi
2019-07-29 13:22 ` Miquel Raynal
2019-07-29 20:00 ` Michael Nazzareno Trimarchi
2019-07-29 21:02 ` Miquel Raynal
2019-07-30 0:28 ` Greg Ungerer
2019-07-30 0:41 ` Greg Ungerer
2019-07-30 6:06 ` Greg Ungerer
2019-07-30 8:38 ` Miquel Raynal
2019-07-30 8:58 ` Boris Brezillon
2019-07-31 2:05 ` Greg Ungerer
2019-07-31 6:28 ` Boris Brezillon
2019-08-02 7:19 ` Greg Ungerer [this message]
2019-08-02 12:34 ` Greg Ungerer
2019-08-02 12:51 ` Boris Brezillon
2019-08-05 5:51 ` Greg Ungerer
2019-08-07 16:05 ` Miquel Raynal
2019-08-08 0:43 ` Greg Ungerer
2019-08-08 16:36 ` Boris Brezillon
2019-08-09 5:20 ` Greg Ungerer
2019-08-09 6:23 ` Boris Brezillon
2019-08-09 6:55 ` Greg Ungerer
2019-08-09 7:32 ` Boris Brezillon
2019-08-09 13:57 ` Greg Ungerer
2019-08-09 13:59 ` Boris Brezillon
2019-08-12 2:50 ` Greg Ungerer
2019-08-12 4:04 ` Greg Ungerer
2019-08-12 7:31 ` Boris Brezillon
2019-08-13 0:50 ` Greg Ungerer
2021-01-28 9:45 ` Michael Nazzareno Trimarchi
2021-01-28 10:26 ` Miquel Raynal
2021-01-28 10:35 ` Michael Nazzareno Trimarchi
2021-01-28 11:55 ` Michael Nazzareno Trimarchi
2021-01-29 12:43 ` Greg Ungerer
2021-01-30 9:41 ` Michael Nazzareno Trimarchi
2021-02-01 14:13 ` Miquel Raynal
2021-02-01 14:32 ` Michael Nazzareno Trimarchi
2021-02-01 15:08 ` Michael Nazzareno Trimarchi
2021-02-01 15:14 ` Miquel Raynal
2021-02-01 15:17 ` Michael Nazzareno Trimarchi
2021-10-15 20:05 ` Michael Trimarchi
2021-10-15 20:12 ` Michael Nazzareno Trimarchi
2021-10-18 7:19 ` Miquel Raynal
2021-10-18 7:33 ` Michael Nazzareno Trimarchi
2021-10-18 7:43 ` Miquel Raynal
2021-10-04 5:54 ` Christian Eggers
2021-10-04 6:27 ` Michael Nazzareno Trimarchi
2021-10-04 15:33 ` Miquel Raynal
2021-10-04 16:06 ` Han Xu
2021-10-05 6:02 ` Christian Eggers
2021-10-08 9:55 ` Christian Eggers
2021-10-08 12:08 ` Stefan Riedmüller
2021-10-08 12:27 ` Miquel Raynal
2021-10-08 13:11 ` Christian Eggers
2021-10-08 13:29 ` Miquel Raynal
2021-10-08 13:36 ` Miquel Raynal
2021-10-08 13:49 ` Christian Eggers
2021-10-08 16:07 ` Miquel Raynal
2021-10-09 5:53 ` Michael Nazzareno Trimarchi
2021-10-11 6:46 ` Miquel Raynal
2021-10-12 9:02 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Stefan Riedmueller
2021-10-12 9:02 ` [RFC PATCH 2/2] gpmi-nand: Add ERR007117 protection for nfc_apply_timings Stefan Riedmueller
2021-10-13 5:01 ` Han Xu
2021-10-22 8:45 ` Stefan Riedmüller
2021-10-22 14:35 ` han.xu
2021-10-25 9:39 ` Stefan Riedmüller
2021-10-28 9:28 ` Stefan Riedmüller
2021-11-01 4:01 ` han.xu
2021-10-13 6:10 ` Christian Eggers
2021-10-13 6:00 ` [RFC PATCH 1/2] mtd: rawnand: gpmi: Remove explicit default gpmi clock setting for i.MX6 Christian Eggers
2021-10-09 6:26 ` GPMI iMX6ull timeout on DMA Christian Eggers
2021-10-13 6:15 ` Christian Eggers
2021-10-08 13:13 ` Christian Eggers
2021-10-08 13:30 ` Miquel Raynal
2021-10-09 6:33 ` Christian Eggers
-- strict thread matches above, loose matches on Subject: below --
2018-10-02 13:22 GPMI IMX6ull timeout on dma Michael Nazzareno Trimarchi
2018-10-04 14:36 ` Michael Nazzareno Trimarchi
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