RE: [PATCH v2] nvme: put some AMD PCIE downstream NVME device to simple suspend/resume path

From: "Liang, Prike" <Prike.Liang@amd.com>
To: Chaitanya Kulkarni <Chaitanya.Kulkarni@wdc.com>,
	Keith Busch <kbusch@kernel.org>
Cc: "linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
	"axboe@fb.com" <axboe@fb.com>, "hch@lst.de" <hch@lst.de>,
	"sagi@grimberg.me" <sagi@grimberg.me>,
	"S-k, Shyam-sundar" <Shyam-sundar.S-k@amd.com>,
	"Deucher,  Alexander" <Alexander.Deucher@amd.com>
Subject: RE: [PATCH v2] nvme: put some AMD PCIE downstream NVME device to simple suspend/resume path
Date: Tue, 6 Apr 2021 07:17:30 +0000	[thread overview]
Message-ID: <BYAPR12MB323843C917E3DD8B78F5B89BFB769@BYAPR12MB3238.namprd12.prod.outlook.com> (raw)
In-Reply-To: <DM6PR04MB49722AA7EB8BC1BE985FCC15867B9@DM6PR04MB4972.namprd04.prod.outlook.com>

[AMD Public Use]

> > This header is not appropriate for public list communication.
>
> Yes please remove this from next patches.
[Prike]  Yeah, the header should be replaced to public info.
>
> >>>> +static const struct pci_device_id pcie_ids[] = { {
> >>>> +PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_RN) }, {
> >>>> +PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_CZN) }, { } };
> >>>> +
> >>> why new global pci_device_id array is needed ?
> >>>
> >> [Prike] This pci_device_id  array contains the platform root complex DID
> which need shutdown the NVME in this armed platform for s2idle.
> > I think Chaitanya is just suggesting you move this declaration to the
> > scope that uses it.
> >
>
[Prike]  Thanks proposal and that's sound good to move the reference PCI ID table into the caller scope directly.

> Yes, something like this on the top of your patch totally untested :-
>
> diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index
> fa81cea41f48..8b2f619eabab 100644
> --- a/drivers/nvme/host/pci.c
> +++ b/drivers/nvme/host/pci.c
> @@ -42,9 +42,6 @@
>  #define NVME_MAX_KB_SZ 4096
>  #define NVME_MAX_SEGS  127
>
> -#define AMD_PCIE_ID_CZN 0x1630
> -#define AMD_PCIE_ID_RN AMD_PCIE_ID_CZN
> -
>  static int use_threaded_interrupts;
>  module_param(use_threaded_interrupts, int, 0);
>
> @@ -73,12 +70,6 @@ static unsigned int io_queue_depth = 1024;
> module_param_cb(io_queue_depth, &io_queue_depth_ops,
> &io_queue_depth, 0644);  MODULE_PARM_DESC(io_queue_depth, "set io
> queue depth, should >= 2");
>
> -static const struct pci_device_id pcie_ids[] = {
> -       { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_RN) },
> -       { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_CZN) },
> -       { }
> -};
> -
>  static int io_queue_count_set(const char *val, const struct kernel_param *kp)
> {
>         unsigned int n;
> @@ -2835,6 +2826,10 @@ static unsigned long
> check_vendor_combination_bug(struct pci_dev *pdev)  }
>
>  #ifdef CONFIG_ACPI
> +
> +#define AMD_PCIE_ID_CZN 0x1630
> +#define AMD_PCIE_ID_RN AMD_PCIE_ID_CZN
> +
>  static bool nvme_acpi_storage_d3(struct pci_dev *dev)  {
>         struct acpi_device *adev;
> @@ -2843,6 +2838,12 @@ static bool nvme_acpi_storage_d3(struct pci_dev
> *dev)
>         acpi_handle handle;
>         acpi_status status;
>         u8 val;
> +       const struct pci_device_id pcie_ids[] = {
> +               { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_RN) },
> +               { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_PCIE_ID_CZN) },
> +               { }
> +       };
> +
>
>         /*
>          * Look for _DSD property specifying that the storage device on the port


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