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From: Vidya Sagar <vidyas@nvidia.com>
To: <bhelgaas@google.com>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>, <kishon@ti.com>,
	<catalin.marinas@arm.com>, <will.deacon@arm.com>,
	<lorenzo.pieralisi@arm.com>, <jingoohan1@gmail.com>,
	<gustavo.pimentel@synopsys.com>, <mperttunen@nvidia.com>
Cc: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH V2 06/16] PCI: dwc: Add ext config space capability search API
Date: Fri, 5 Apr 2019 01:24:33 +0530	[thread overview]
Message-ID: <1554407683-31580-7-git-send-email-vidyas@nvidia.com> (raw)
In-Reply-To: <1554407683-31580-1-git-send-email-vidyas@nvidia.com>

Add extended configuration space capability search API using struct dw_pcie *
pointer

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
Changes from [v1]:
* This is a new patch in v2 series

 drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h |  1 +
 2 files changed, 42 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index d68c123e409c..44c0ba078452 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
 	return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
 }
 
+static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
+					    int cap)
+{
+	u32 header;
+	int ttl;
+	int pos = PCI_CFG_SPACE_SIZE;
+
+	/* minimum 8 bytes per capability */
+	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+	if (start)
+		pos = start;
+
+	header = dw_pcie_readl_dbi(pci, pos);
+	/*
+	 * If we have no capabilities, this is indicated by cap ID,
+	 * cap version and next pointer all being 0.
+	 */
+	if (header == 0)
+		return 0;
+
+	while (ttl-- > 0) {
+		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
+			return pos;
+
+		pos = PCI_EXT_CAP_NEXT(header);
+		if (pos < PCI_CFG_SPACE_SIZE)
+			break;
+
+		header = dw_pcie_readl_dbi(pci, pos);
+	}
+
+	return 0;
+}
+
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
+{
+	return dw_pcie_find_next_ext_capability(pci, 0, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
+
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 4ccd4c706ddb..fa41d675c48f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -248,6 +248,7 @@ struct dw_pcie {
 		container_of((endpoint), struct dw_pcie, ep)
 
 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
 
 int dw_pcie_read(void __iomem *addr, int size, u32 *val);
 int dw_pcie_write(void __iomem *addr, int size, u32 val);
-- 
2.7.4


  parent reply	other threads:[~2019-04-04 19:55 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-04 19:54 [PATCH V2 00/16] Add Tegra194 PCIe support Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 01/16] PCI: Add #defines for PCIe spec r4.0 features Vidya Sagar
2019-04-11 10:13   ` Thierry Reding
2019-04-16 13:15     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 02/16] PCI/PME: Export pcie_pme_disable_msi() API Vidya Sagar
2019-04-11 10:16   ` Thierry Reding
2019-04-16 13:30     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 03/16] PCI: Export pcie_bus_config symbol Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 04/16] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 05/16] PCI: dwc: Move config space capability search API Vidya Sagar
2019-04-04 19:54 ` Vidya Sagar [this message]
2019-04-04 19:54 ` [PATCH V2 07/16] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-04-15 14:54   ` Thierry Reding
2019-04-16 14:29     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 08/16] PCI: dwc: Add support to enable " Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 09/16] Documentation/devicetree: Add PCIe supports-clkreq property Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 10/16] dt-bindings: PCI: tegra: Add device tree support for T194 Vidya Sagar
2019-04-15 15:08   ` Thierry Reding
2019-04-16 15:33     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 11/16] dt-bindings: PHY: P2U: Add Tegra 194 P2U block Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Vidya Sagar
2019-04-15 15:15   ` Thierry Reding
2019-04-16 17:48     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 13/16] arm64: tegra: Enable PCIe slots in P2972-0000 board Vidya Sagar
2019-04-15 15:12   ` Thierry Reding
2019-04-16 17:55     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 14/16] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-04-15 15:31   ` Thierry Reding
2019-04-15 15:33     ` Thierry Reding
2019-04-16 18:14     ` Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 15/16] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-04-04 19:54 ` [PATCH V2 16/16] arm64: Add Tegra194 PCIe driver to defconfig Vidya Sagar

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