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* Re: PCIe PASID (Process Address Space ID) and iommu code
       [not found] <CA+QbAV6-C9wxPttEx0uDn_K5Y1LaGt8pxDWc8RJmN4DqR+NHtQ@mail.gmail.com>
@ 2014-10-16  3:50 ` Bjorn Helgaas
  2014-10-16  9:14   ` Joerg Roedel
  0 siblings, 1 reply; 2+ messages in thread
From: Bjorn Helgaas @ 2014-10-16  3:50 UTC (permalink / raw)
  To: Kallol Biswas
  Cc: linux-kernel, linux-pci, Joerg Roedel,
	open list:INTEL IOMMU (VT-d),
	Suravee Suthikulpanit, Jay Cornwall

[+cc Joerg, Suravee, Jay, iommu list, linux-pci]

On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne@gmail.com> wrote:
> Resending, as message got bounced for html content.
> --------------------------------------------
> Hi,
>     PCIe has introduced PASID TLP Prefix.  There are two ECNs on this.
>
> It seems that AMD iommu code makes use of PASID. Is there a device that
> utilizes this TLP prefix?
>
> PASID allocation and management within a device is not clear to me. How
> does device know which PASID to issue for which virtual address? Who makes
> the association? Must be software/OS, but how? There is no table for this
> like MSI-X table.
>
> Any pointer/documentation will be appreciated.
>
> Regards,
> --
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^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: PCIe PASID (Process Address Space ID) and iommu code
  2014-10-16  3:50 ` PCIe PASID (Process Address Space ID) and iommu code Bjorn Helgaas
@ 2014-10-16  9:14   ` Joerg Roedel
  0 siblings, 0 replies; 2+ messages in thread
From: Joerg Roedel @ 2014-10-16  9:14 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: Kallol Biswas, linux-kernel, linux-pci,
	open list:INTEL IOMMU (VT-d),
	Suravee Suthikulpanit, Jay Cornwall

On Wed, Oct 15, 2014 at 09:50:58PM -0600, Bjorn Helgaas wrote:
> [+cc Joerg, Suravee, Jay, iommu list, linux-pci]
> 
> On Wed, Oct 15, 2014 at 5:44 PM, Kallol Biswas <nucleodyne@gmail.com> wrote:
> > Resending, as message got bounced for html content.
> > --------------------------------------------
> > Hi,
> >     PCIe has introduced PASID TLP Prefix.  There are two ECNs on this.
> >
> > It seems that AMD iommu code makes use of PASID. Is there a device that
> > utilizes this TLP prefix?

Yes, recent radeon GPUs can make use of the TLP prefix.

> > PASID allocation and management within a device is not clear to me. How
> > does device know which PASID to issue for which virtual address? Who makes
> > the association? Must be software/OS, but how? There is no table for this
> > like MSI-X table.

The setup of the PASIDs is device specific, so there is no standard for
setting up PASID address spaces on devices.


HTH,

	Joerg


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2014-10-16  3:50 ` PCIe PASID (Process Address Space ID) and iommu code Bjorn Helgaas
2014-10-16  9:14   ` Joerg Roedel

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