From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, Vidya Sagar <vidyas@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Subject: Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
Date: Tue, 3 Nov 2020 16:24:41 +0000 [thread overview]
Message-ID: <20201103162441.GA2415@e121166-lin.cambridge.arm.com> (raw)
In-Reply-To: <20201026154852.221483-1-robh@kernel.org>
On Mon, Oct 26, 2020 at 10:48:52AM -0500, Rob Herring wrote:
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
>
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
Bjorn, this is v5.10 material please pick it up for one of the
upcoming -rc*:
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> * ATU, so we should not program the ATU here.
> */
> if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> - struct resource_entry *entry =
> - resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> + struct resource_entry *tmp, *entry = NULL;
> +
> + /* Get last memory resource entry */
> + resource_list_for_each_entry(tmp, &pp->bridge->windows)
> + if (resource_type(tmp->res) == IORESOURCE_MEM)
> + entry = tmp;
>
> dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
> PCIE_ATU_TYPE_MEM, entry->res->start,
> --
> 2.25.1
>
next prev parent reply other threads:[~2020-11-03 16:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
2020-10-26 16:22 ` Jingoo Han
2020-10-26 16:49 ` Vidya Sagar
2020-10-26 18:02 ` Rob Herring
2020-11-03 16:24 ` Lorenzo Pieralisi [this message]
2020-11-03 19:30 ` Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201103162441.GA2415@e121166-lin.cambridge.arm.com \
--to=lorenzo.pieralisi@arm.com \
--cc=bhelgaas@google.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=linux-pci@vger.kernel.org \
--cc=robh@kernel.org \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).