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From: "Marek Behún" <kabel@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	linux-pci@vger.kernel.org, pali@kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH 06/13] PCI: aardvark: Do not clear status bits of masked interrupts
Date: Tue, 5 Oct 2021 14:13:40 +0200	[thread overview]
Message-ID: <20211005141340.48c8c0f6@dellmb> (raw)
In-Reply-To: <871r50st5h.wl-maz@kernel.org>

On Mon, 04 Oct 2021 16:31:54 +0100
Marc Zyngier <maz@kernel.org> wrote:

> On Mon, 04 Oct 2021 15:06:53 +0100,
> Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> > 
> > [+Marc - always better to have his eyes on IRQ handling code]
> > 
> > On Fri, Oct 01, 2021 at 09:58:49PM +0200, Marek Behún wrote:  
> > > From: Pali Rohár <pali@kernel.org>
> > > 
> > > It is incorrect to clear status bits of masked interrupts.
> > > 
> > > The aardvark driver clears all status interrupt bits if no
> > > unmasked status bit is set. Masked bits should never be cleared.
> > > 
> > > Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host
> > > controller driver") Signed-off-by: Pali Rohár <pali@kernel.org>
> > > Reviewed-by: Marek Behún <kabel@kernel.org>
> > > Signed-off-by: Marek Behún <kabel@kernel.org>
> > > Cc: stable@vger.kernel.org
> > > ---
> > >  drivers/pci/controller/pci-aardvark.c | 5 +----
> > >  1 file changed, 1 insertion(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/pci/controller/pci-aardvark.c
> > > b/drivers/pci/controller/pci-aardvark.c index
> > > d5d6f92e5143..e4986806a189 100644 ---
> > > a/drivers/pci/controller/pci-aardvark.c +++
> > > b/drivers/pci/controller/pci-aardvark.c @@ -1295,11 +1295,8 @@
> > > static void advk_pcie_handle_int(struct advk_pcie *pcie)
> > > isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); isr1_status =
> > > isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 
> > > -	if (!isr0_status && !isr1_status) {
> > > -		advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
> > > -		advk_writel(pcie, isr1_val, PCIE_ISR1_REG);  
> > 
> > This looks fine - on the other hand if no interrupt is set in the
> > status registers (that are filtered with the masks) we are dealing
> > with a spurious IRQ right ? Just gauging how severe this is.
> > 
> > Lorenzo
> >   
> > > +	if (!isr0_status && !isr1_status)
> > >  		return;  
> 
> The whole thing is a bit odd. What the commit message doesn't say is
> whether the status register shows the status of the line before
> masking, or after masking.

I don't quite understand what you are asking about.
If you are asking about the register itself:
the PCIE_ISR1_REG says which interrupts are currently set / active,
including those which are masked.

If you are asking about the isr1_status variable, it is the
status of the line after masking. I.e. masked interrupts are not set in
this variable, only active interrupts which are also unmasked. That is
obvious from the code.

> The code seems to imply the former, but then the behaviour is
> awkward. How did we end-up here the first place?

I answered this in reply to Lorenzo's comment on this patch, see
https://lore.kernel.org/linux-pci/20211004171823.0288684e@thinkpad/

> if that's only a
> spurious interrupt, then I'd probably simplify the code altogether,
> and drop all the early return code. Something like below, as usual
> completely untested.
> 
> 	M.
> 
> diff --git a/drivers/pci/controller/pci-aardvark.c
> b/drivers/pci/controller/pci-aardvark.c index
> 596ebcfcc82d..1d8f257ecb63 100644 ---
> a/drivers/pci/controller/pci-aardvark.c +++
> b/drivers/pci/controller/pci-aardvark.c @@ -1275,7 +1275,8 @@ static
> void advk_pcie_handle_msi(struct advk_pcie *pcie) static void
> advk_pcie_handle_int(struct advk_pcie *pcie) {
>  	u32 isr0_val, isr0_mask, isr0_status;
> -	u32 isr1_val, isr1_mask, isr1_status;
> +	u32 isr1_val, isr1_mask;
> +	unsigned long isr1_status;
>  	int i;
>  
>  	isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
> @@ -1285,22 +1286,14 @@ static void advk_pcie_handle_int(struct
> advk_pcie *pcie) isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
>  	isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
>  	isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
> -
> -	if (!isr0_status && !isr1_status) {
> -		advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
> -		advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
> -		return;
> -	}
> +	isr1_status >> 8;
>
>  	/* Process MSI interrupts */
>  	if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
>  		advk_pcie_handle_msi(pcie);
>  
>  	/* Process legacy interrupts */
> -	for (i = 0; i < PCI_NUM_INTX; i++) {
> -		if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
> -			continue;
> -
> +	for_each_set_bit(i, &isr1_status, PCI_NUM_INTX) {
>  		advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
>  			    PCIE_ISR1_REG);

1. what you are doing here is code cleanup. We are currently in the
   state where we have lots of fixes for this driver, which we are
   hoping will go also to stable. Some of them depend on these changes.
   Can we please first apply those fixes (we want to send them in
   batches to avoid sending 60 patchs in one series, since last time
   nobody wanted to review all of that) and do this afterwards?

2. you are throwing away lower 8 bits of isr1_status. We have follow-up
   patches (not in this series, but in another batch which we want to
   send after this) that will be using those lower 8 bits, so we do not
   want to throw away them now.

Marek

PS: You can look at all the prepared changes at
https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git/log/?h=pci-aardvark

  reply	other threads:[~2021-10-05 12:13 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-01 19:58 [PATCH 00/13] PCI: aardvark controller fixes Marek Behún
2021-10-01 19:58 ` [PATCH 01/13] PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros Marek Behún
2021-10-02 16:05   ` Bjorn Helgaas
2021-10-04  8:43   ` Lorenzo Pieralisi
2021-10-04  9:32     ` Marek Behún
2021-10-04  9:35       ` Lorenzo Pieralisi
2021-10-01 19:58 ` [PATCH 02/13] PCI: aardvark: Fix PCIe Max Payload Size setting Marek Behún
2021-10-03 17:44   ` Marek Behún
2021-10-01 19:58 ` [PATCH 03/13] PCI: aardvark: Don't spam about PIO Response Status Marek Behún
2021-10-01 19:58 ` [PATCH 04/13] PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge Marek Behún
2021-10-01 19:58 ` [PATCH 05/13] PCI: aardvark: Fix configuring Reference clock Marek Behún
2021-10-01 19:58 ` [PATCH 06/13] PCI: aardvark: Do not clear status bits of masked interrupts Marek Behún
2021-10-04 14:06   ` Lorenzo Pieralisi
2021-10-04 15:18     ` Marek Behún
2021-10-04 15:31     ` Marc Zyngier
2021-10-05 12:13       ` Marek Behún [this message]
2021-10-05 12:42         ` Marc Zyngier
2021-10-05 13:15           ` Pali Rohár
2021-10-05 15:42             ` Marc Zyngier
2021-10-05 18:48               ` Pali Rohár
2021-10-05 16:04             ` Lorenzo Pieralisi
2021-10-01 19:58 ` [PATCH 07/13] PCI: aardvark: Do not unmask unused interrupts Marek Behún
2021-10-01 19:58 ` [PATCH 08/13] PCI: aardvark: Deduplicate code in advk_pcie_rd_conf() Marek Behún
2021-10-01 19:58 ` [PATCH 09/13] PCI: aardvark: Implement re-issuing config requests on CRS response Marek Behún
2021-10-02 16:35   ` Bjorn Helgaas
2021-10-04  7:21     ` Marek Behún
2021-10-04  8:53       ` Lorenzo Pieralisi
2021-10-04 10:19         ` Marek Behún
2021-10-05 19:28           ` Bjorn Helgaas
2021-10-05 22:45             ` Marek Behún
2021-10-11 18:15               ` Usage of PCBIOS_* macros (Was: Re: [PATCH 09/13] PCI: aardvark: Implement re-issuing config requests on CRS response) Pali Rohár
2021-10-11 20:58                 ` Bjorn Helgaas
2021-10-06 16:29             ` [PATCH 09/13] PCI: aardvark: Implement re-issuing config requests on CRS response Lorenzo Pieralisi
2021-10-06 20:13               ` Bjorn Helgaas
2021-10-07 11:51                 ` Lorenzo Pieralisi
2021-10-07 12:36                   ` Marek Behún
2021-10-07 19:25                     ` Bjorn Helgaas
2021-10-01 19:58 ` [PATCH 10/13] PCI: aardvark: Simplify initialization of rootcap on virtual bridge Marek Behún
2021-10-04  9:44   ` Lorenzo Pieralisi
2021-10-04  9:56     ` Marek Behún
2021-10-04 10:10       ` Lorenzo Pieralisi
2021-10-01 19:58 ` [PATCH 11/13] PCI: aardvark: Fix link training Marek Behún
2021-10-01 19:58 ` [PATCH 12/13] PCI: aardvark: Fix checking for link up via LTSSM state Marek Behún
2021-10-04 13:35   ` Lorenzo Pieralisi
2021-10-01 19:58 ` [PATCH 13/13] PCI: aardvark: Fix reporting Data Link Layer Link Active Marek Behún
2021-10-04  9:53 ` [PATCH 00/13] PCI: aardvark controller fixes Lorenzo Pieralisi
2021-10-04 10:40   ` Marek Behún

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