* [RESEND#2 PATCH v4] MAINTAINERS: add polarfire rng, pci and clock drivers
@ 2022-07-07 14:20 Conor Dooley
0 siblings, 0 replies; only message in thread
From: Conor Dooley @ 2022-07-07 14:20 UTC (permalink / raw)
To: soc
Cc: conor.dooley, Cyril.Jean, Daire.McNamara, Lewis.Hanly, aou, arnd,
bhelgaas, herbert, linux-clk, linux-kernel, linux-pci,
linux-riscv, lorenzo.pieralisi, mturquette, sboyd, palmer,
palmer, paul.walmsley
Hardware random, PCI and clock drivers for the PolarFire SoC have been
upstreamed but are not covered by the MAINTAINERS entry, so add them.
Daire is the author of the clock & PCI drivers, so add him as a
maintainer in place of Lewis.
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Resending with +CC soc@kernel.org
It's a v4 because the other patches were applied/dropped.
MAINTAINERS | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a6d3bd9d2a8d..01a7bfa49bdc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17136,12 +17136,15 @@ N: riscv
K: riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
-M: Lewis Hanly <lewis.hanly@microchip.com>
M: Conor Dooley <conor.dooley@microchip.com>
+M: Daire McNamara <daire.mcnamara@microchip.com>
L: linux-riscv@lists.infradead.org
S: Supported
F: arch/riscv/boot/dts/microchip/
+F: drivers/char/hw_random/mpfs-rng.c
+F: drivers/clk/microchip/clk-mpfs.c
F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/pci/controller/pcie-microchip-host.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.36.1
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