From: Wangseok Lee <wangseok.lee@samsung.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: "robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"kishon@ti.com" <kishon@ti.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"jesper.nilsson@axis.com" <jesper.nilsson@axis.com>,
"lars.persson@axis.com" <lars.persson@axis.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"linux-phy@lists.infradead.org" <linux-phy@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"kw@linux.com" <kw@linux.com>,
"linux-arm-kernel@axis.com" <linux-arm-kernel@axis.com>,
"kernel@axis.com" <kernel@axis.com>,
Moon-Ki Jun <moonki.jun@samsung.com>,
Sang Min Kim <hypmean.kim@samsung.com>,
Dongjin Yang <dj76.yang@samsung.com>,
Yeeun Kim <yeeun119.kim@samsung.com>
Subject: Re: [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver
Date: Thu, 14 Jul 2022 18:59:55 +0900 [thread overview]
Message-ID: <20220714095955epcms2p5f5e9a3123a368069b5c661cdeb70485e@epcms2p5> (raw)
In-Reply-To: <YsW9m6hotDKacXe3@matsya>
On 07-07-22, 01:52, Vinod Koul wrote:
> On 06-07-22, 17:10, Wangseok Lee wrote:
>> On 05-07-22, 15:30, Vinod Koul wrote:
>> > On 14-06-22, 10:34, Wangseok Lee wrote:
>> >> Add support Axis, ARTPEC-8 SoC.
>> >> ARTPEC-8 is the SoC platform of Axis Communications.
>> >> This is based on arm64 and support GEN4 & 2lane.
>> >> This driver provides PHY interface for ARTPEC-8 SoC PCIe controller,
>> >> based on Samsung PCIe PHY IP.
>> >>
>> >> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
>> >> Signed-off-by: Jaeho Cho <jaeho79.cho@samsung.com>
>> >> ---
>> >> v2->v3 :
>> >> -remove unnecessary indentation
>> >> -redefine local struct to statis const
>> >> -add static const to struct that requires static const definition
>> >> -remove wrappers on writel and readl
>> >>
>> >> v1->v2 :
>> >> -change folder name of phy driver to axis from artpec
>> >> ---
>> >> drivers/phy/Kconfig | 1 +
>> >> drivers/phy/Makefile | 1 +
>> >> drivers/phy/axis/Kconfig | 9 +
>> >> drivers/phy/axis/Makefile | 2 +
>> >> drivers/phy/axis/phy-artpec8-pcie.c | 776 ++++++++++++++++++++++++++++++++++++
>> >> 5 files changed, 789 insertions(+)
>> >> create mode 100644 drivers/phy/axis/Kconfig
>> >> create mode 100644 drivers/phy/axis/Makefile
>> >> create mode 100644 drivers/phy/axis/phy-artpec8-pcie.c
>> >>
>> >> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> >> index 300b0f2..92b8232 100644
>> >> --- a/drivers/phy/Kconfig
>> >> +++ b/drivers/phy/Kconfig
>> >> @@ -73,6 +73,7 @@ config PHY_CAN_TRANSCEIVER
>> >>
>> >> source "drivers/phy/allwinner/Kconfig"
>> >> source "drivers/phy/amlogic/Kconfig"
>> >> +source "drivers/phy/axis/Kconfig"
>> >> source "drivers/phy/broadcom/Kconfig"
>> >> source "drivers/phy/cadence/Kconfig"
>> >> source "drivers/phy/freescale/Kconfig"
>> >> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> >> index 01e9eff..808c055e 100644
>> >> --- a/drivers/phy/Makefile
>> >> +++ b/drivers/phy/Makefile
>> >> @@ -12,6 +12,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
>> >> obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
>> >> obj-y += allwinner/ \
>> >> amlogic/ \
>> >> + axis/ \
>> >> broadcom/ \
>> >> cadence/ \
>> >> freescale/ \
>> >> diff --git a/drivers/phy/axis/Kconfig b/drivers/phy/axis/Kconfig
>> >> new file mode 100644
>> >> index 0000000..7198b93
>> >> --- /dev/null
>> >> +++ b/drivers/phy/axis/Kconfig
>> >> @@ -0,0 +1,9 @@
>> >> +config PHY_ARTPEC8_PCIE
>> >> + bool "ARTPEC-8 PCIe PHY driver"
>> >> + depends on OF && (ARCH_ARTPEC8 || COMPILE_TEST)
>> >> + select GENERIC_PHY
>> >> + help
>> >> + Enable PCIe PHY support for ARTPEC-8 SoC.
>> >> + This driver provides PHY interface for ARTPEC-8 SoC
>> >> + PCIe controller.
>> >> + This is based on Samsung PCIe PHY IP.
>> >
>> > How different is it from SS IP and why should it not be under
>> > phy/samsung/ then?
>> >
>>
>> SoC platform is completely different from exynos platform and different
>> from exynos PCIe PHY. So the overall sysreg configuration is different
>> and register map is also different. The reset method and type of PHY for
>> initialization are different. This is not a driver that supports Samsung
>> SoC platform, but this PHY driver that supports only Axis, Artpec-8
>> platforms, so it is not added to phy/samsung.
>
> SoC is a moot point. If the IP block is same then we should try to reuse
> the existing phy driver, modifications to current driver to support your
> changes should be fine...
>
> Is that feasible?
>
> --
> ~Vinod
Sorry for late reply.
Above all, the IP blocks of phy-exynos-pcie.c and artpec8's pcie phy are
different. As a result, the H/W architecture and operation sequence is
very different. So it is very difficult to merge into a exynos pcie file.
If possible, we would like to proceed with a new file. Is that possible?
Best regards,
Wangseok Lee
next prev parent reply other threads:[~2022-07-14 10:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p7>
2022-06-14 1:16 ` [PATCH v3 0/5] Add support for Axis, ARTPEC-8 PCIe driver Wangseok Lee
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p3>
2022-06-14 1:30 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-06-20 8:35 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p8>
2022-06-14 1:27 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-16 22:54 ` Krzysztof Kozlowski
2022-06-14 1:34 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-05 6:21 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p6>
2022-06-14 1:36 ` [PATCH v3 5/5] MAINTAINERS: Add Axis ARTPEC-8 PCIe PHY maintainers Wangseok Lee
2022-06-20 7:55 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-20 8:42 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p2>
2022-06-21 7:42 ` Wangseok Lee
2022-06-21 12:44 ` Krzysztof Kozlowski
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p4>
2022-06-22 7:20 ` Wangseok Lee
2022-07-06 5:22 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-07-06 6:28 ` Krzysztof Kozlowski
2022-06-29 7:18 ` Wangseok Lee
2022-07-05 10:56 ` Krzysztof Kozlowski
2022-07-06 8:10 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Wangseok Lee
2022-07-06 16:51 ` Vinod Koul
[not found] ` <CGME20220614011616epcms2p7dcaa67c53b7df5802dd7a697e2d472d7@epcms2p5>
2022-06-14 1:29 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
2022-06-16 22:58 ` Krzysztof Kozlowski
2022-06-20 8:38 ` Wangseok Lee
2022-06-21 21:13 ` Bjorn Helgaas
[not found] ` <CGME20220621212357epcas2p41ecf1ace5d207b154cc77dac79bc7e53@epcms2p2>
2022-06-22 7:06 ` Wangseok Lee
2022-06-22 7:21 ` [PATCH v3 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Wangseok Lee
2022-06-23 8:27 ` Krzysztof Kozlowski
2022-07-14 9:59 ` Wangseok Lee [this message]
2022-07-15 11:33 ` [PATCH v3 4/5] phy: Add ARTPEC-8 PCIe PHY driver Vinod Koul
2022-06-21 7:56 ` [PATCH v3 3/5] PCI: axis: Add ARTPEC-8 PCIe controller driver Wangseok Lee
2022-07-06 5:20 ` [PATCH v3 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy Wangseok Lee
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