From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org
Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
konrad.dybcio@somainline.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
dmitry.baryshkov@linaro.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 04/11] PCI: qcom-ep: Add eDMA support
Date: Fri, 26 Aug 2022 23:49:16 +0530 [thread overview]
Message-ID: <20220826181923.251564-5-manivannan.sadhasivam@linaro.org> (raw)
In-Reply-To: <20220826181923.251564-1-manivannan.sadhasivam@linaro.org>
Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA)
peripheral for offloading the data transfer between PCIe bus and memory.
Let's add the support for it by enabling the eDMA IRQ in the driver.
Rest of the functionality will be handled by the eDMA DMA Engine driver.
Since the eDMA on Qualcomm platforms only uses a single IRQ for all
channels, use 1 for edma.nr_irqs.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 1e09eca5b3b2..54b927adf60a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -66,6 +66,7 @@
#define PARF_INT_ALL_PLS_ERR BIT(15)
#define PARF_INT_ALL_PME_LEGACY BIT(16)
#define PARF_INT_ALL_PLS_PME BIT(17)
+#define PARF_INT_ALL_EDMA BIT(22)
/* PARF_BDF_TO_SID_CFG register fields */
#define PARF_BDF_TO_SID_BYPASS BIT(0)
@@ -367,7 +368,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
- PARF_INT_ALL_LINK_UP;
+ PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
@@ -670,6 +671,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
pcie_ep->pci.dev = dev;
pcie_ep->pci.ops = &pci_ops;
pcie_ep->pci.ep.ops = &pci_ep_ops;
+ pcie_ep->pci.edma.nr_irqs = 1;
platform_set_drvdata(pdev, pcie_ep);
ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
--
2.25.1
next prev parent reply other threads:[~2022-08-26 18:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-26 18:19 [PATCH 00/11] Improvements to the Qcom PCIe Endpoint driver Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 01/11] PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 02/11] PCI: qcom-ep: Do not use hardcoded clks in driver Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 03/11] PCI: qcom-ep: Make use of the cached dev pointer Manivannan Sadhasivam
2022-08-26 18:19 ` Manivannan Sadhasivam [this message]
2022-08-26 18:19 ` [PATCH 05/11] PCI: qcom-ep: Disable IRQs during driver remove Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 06/11] PCI: qcom-ep: Add debugfs support for expose link transition counts Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 07/11] dt-bindings: PCI: qcom-ep: Make PERST separation optional Manivannan Sadhasivam
2022-08-28 15:12 ` Krzysztof Kozlowski
2022-08-26 18:19 ` [PATCH 08/11] " Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 09/11] dt-bindings: PCI: qcom-ep: Define clocks per platform Manivannan Sadhasivam
2022-08-28 15:14 ` Krzysztof Kozlowski
2022-08-28 15:20 ` Krzysztof Kozlowski
2022-08-30 11:56 ` Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 10/11] dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC Manivannan Sadhasivam
2022-08-28 14:21 ` Rob Herring
2022-08-28 15:17 ` Krzysztof Kozlowski
2022-08-30 11:57 ` Manivannan Sadhasivam
2022-08-26 18:19 ` [PATCH 11/11] " Manivannan Sadhasivam
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