From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
To: linux-arm-msm@vger.kernel.org
Cc: konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
martin.botka@somainline.org, phone-devel@vger.kernel.org,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
rjw@rjwysocki.net, viresh.kumar@linaro.org, nks@flawful.org,
agross@kernel.org, bjorn.andersson@linaro.org,
daniel.lezcano@linaro.org, manivannan.sadhasivam@linaro.org,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>
Subject: [PATCH v3 08/15] arm64: qcom: qcs404: Change CPR nvmem-names
Date: Tue, 12 Jan 2021 19:20:45 +0100 [thread overview]
Message-ID: <20210112182052.481888-9-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210112182052.481888-1-angelogioacchino.delregno@somainline.org>
The CPR driver's common functions were split and put in another
file in order to support newer CPR revisions: to simplify the
commonization, the expected names of the fuses had to be changed
in order for both new and old support to use the same fuse name
retrieval function and keeping the naming consistent.
The thread id was added to the fuse name and, since CPRv1 does
not support threads, it is expected to always read ID 0, which
means that the expected name here is now "cpr0_(fuse_name)"
instead of "cpr_(fuse_name)": luckily, QCS404 is the only user
so change it accordingly.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 339790ba585d..f9350b028435 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1168,19 +1168,19 @@ cpr: power-controller@b018000 {
<&cpr_efuse_ring2>,
<&cpr_efuse_ring3>,
<&cpr_efuse_revision>;
- nvmem-cell-names = "cpr_quotient_offset1",
- "cpr_quotient_offset2",
- "cpr_quotient_offset3",
- "cpr_init_voltage1",
- "cpr_init_voltage2",
- "cpr_init_voltage3",
- "cpr_quotient1",
- "cpr_quotient2",
- "cpr_quotient3",
- "cpr_ring_osc1",
- "cpr_ring_osc2",
- "cpr_ring_osc3",
- "cpr_fuse_revision";
+ nvmem-cell-names = "cpr0_quotient_offset1",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_fuse_revision";
};
timer@b120000 {
--
2.29.2
next prev parent reply other threads:[~2021-01-12 18:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-12 18:20 [PATCH v3 00/15] Enable CPRh/3/4, CPU Scaling on various QCOM SoCs AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 01/15] cpuidle: qcom_spm: Detach state machine from main SPM handling AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 02/15] soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 03/15] soc: qcom: spm: Add compatible for MSM8998 SAWv4.1 L2 AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 04/15] cpufreq: blacklist SDM630/636/660 in cpufreq-dt-platdev AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 05/15] cpufreq: blacklist MSM8998 " AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 06/15] soc: qcom: cpr: Move common functions to new file AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 07/15] dt-bindings: avs: cpr: Convert binding to YAML schema AngeloGioacchino Del Regno
2021-01-12 18:20 ` AngeloGioacchino Del Regno [this message]
2021-01-12 18:20 ` [PATCH v3 09/15] soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 10/15] MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 11/15] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 12/15] dt-bindings: arm: cpus: Document 'qcom,freq-domain' property AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 13/15] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 14/15] cpufreq: qcom-hw: Implement CPRh aware OSM programming AngeloGioacchino Del Regno
2021-01-12 18:20 ` [PATCH v3 15/15] dt-bindings: cpufreq: qcom-hw: Add bindings for 8998 AngeloGioacchino Del Regno
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210112182052.481888-9-angelogioacchino.delregno@somainline.org \
--to=angelogioacchino.delregno@somainline.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@somainline.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=manivannan.sadhasivam@linaro.org \
--cc=marijn.suijten@somainline.org \
--cc=martin.botka@somainline.org \
--cc=nks@flawful.org \
--cc=phone-devel@vger.kernel.org \
--cc=rjw@rjwysocki.net \
--cc=robh+dt@kernel.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).