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From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: horms@verge.net.au, geert@linux-m68k.org,
	khiem.nguyen.xt@renesas.com, dien.pham.ry@renesas.com,
	takeshi.kihara.df@renesas.com,
	Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores
Date: Fri, 18 Jan 2019 11:47:51 +0100	[thread overview]
Message-ID: <1547808474-19427-3-git-send-email-uli+renesas@fpond.eu> (raw)
In-Reply-To: <1547808474-19427-1-git-send-email-uli+renesas@fpond.eu>

From: Dien Pham <dien.pham.ry@renesas.com>

Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7ae974d..483ba3b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -211,6 +211,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -223,6 +224,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -235,6 +237,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -247,6 +250,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -277,6 +281,15 @@
 				exit-latency-us = <500>;
 				min-residency-us = <4000>;
 			};
+
+			CPU_SLEEP_1: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <700>;
+				exit-latency-us = <700>;
+				min-residency-us = <5000>;
+			};
 		};
 	};
 
-- 
2.7.4


  parent reply	other threads:[~2019-01-18 10:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-18 10:47 [PATCH v2 0/5] H3/M3-W cpuidle support Ulrich Hecht
2019-01-18 10:47 ` [PATCH v2 1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores Ulrich Hecht
2019-08-28 11:47   ` Geert Uytterhoeven
2019-01-18 10:47 ` Ulrich Hecht [this message]
     [not found]   ` <20190726091325.GA13111@vmlxhi-102.adit-jv.com>
2019-07-26  9:47     ` [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores Eugeniu Rosca
2019-07-29  7:44       ` Geert Uytterhoeven
2019-07-29 11:32         ` Lorenzo Pieralisi
2019-07-29 21:55           ` Eugeniu Rosca
2019-08-28 11:48   ` Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 3/5] arm64: dts: r8a7796: Add cpuidle support for CA57 cores Ulrich Hecht
2019-08-28 11:48   ` Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores Ulrich Hecht
2019-08-28 11:48   ` Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 5/5] arm64: dts: r8a7796-m3ulcb: Disable " Ulrich Hecht
2019-08-28 12:04 ` [PATCH v2 0/5] H3/M3-W cpuidle support Geert Uytterhoeven
2019-09-03 12:10   ` Geert Uytterhoeven

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