From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: horms@verge.net.au, geert@linux-m68k.org,
khiem.nguyen.xt@renesas.com, dien.pham.ry@renesas.com,
takeshi.kihara.df@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>
Subject: [PATCH v2 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores
Date: Fri, 18 Jan 2019 11:47:53 +0100 [thread overview]
Message-ID: <1547808474-19427-5-git-send-email-uli+renesas@fpond.eu> (raw)
In-Reply-To: <1547808474-19427-1-git-send-email-uli+renesas@fpond.eu>
From: Dien Pham <dien.pham.ry@renesas.com>
Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 212ffd6..81af1ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -188,6 +188,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -200,6 +201,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -212,6 +214,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -224,6 +227,7 @@
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_1>;
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
operating-points-v2 = <&cluster1_opp>;
capacity-dmips-mhz = <535>;
@@ -254,6 +258,15 @@
exit-latency-us = <500>;
min-residency-us = <4000>;
};
+
+ CPU_SLEEP_1: cpu-sleep-1 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <700>;
+ exit-latency-us = <700>;
+ min-residency-us = <5000>;
+ };
};
};
--
2.7.4
next prev parent reply other threads:[~2019-01-18 10:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 10:47 [PATCH v2 0/5] H3/M3-W cpuidle support Ulrich Hecht
2019-01-18 10:47 ` [PATCH v2 1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores Ulrich Hecht
2019-08-28 11:47 ` Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores Ulrich Hecht
[not found] ` <20190726091325.GA13111@vmlxhi-102.adit-jv.com>
2019-07-26 9:47 ` Eugeniu Rosca
2019-07-29 7:44 ` Geert Uytterhoeven
2019-07-29 11:32 ` Lorenzo Pieralisi
2019-07-29 21:55 ` Eugeniu Rosca
2019-08-28 11:48 ` Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 3/5] arm64: dts: r8a7796: Add cpuidle support for CA57 cores Ulrich Hecht
2019-08-28 11:48 ` Geert Uytterhoeven
2019-01-18 10:47 ` Ulrich Hecht [this message]
2019-08-28 11:48 ` [PATCH v2 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores Geert Uytterhoeven
2019-01-18 10:47 ` [PATCH v2 5/5] arm64: dts: r8a7796-m3ulcb: Disable " Ulrich Hecht
2019-08-28 12:04 ` [PATCH v2 0/5] H3/M3-W cpuidle support Geert Uytterhoeven
2019-09-03 12:10 ` Geert Uytterhoeven
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