[PATCH] clk: renesas: r8a77990: Add Z2 clock

[PATCH] clk: renesas: r8a77990: Add Z2 clock

[Simon Horman]

Adds Z2 clock to CPG driver for the R-Car E3 (r8a77990) SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

 Tested on top of renesas-devel-20190128-v5.0-rc4
 in conjunction with 
 "[PATCH/RFT] arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices"

 https://patchwork.kernel.org/patch/10764359/

 Test results to be posted to that thread shortly.

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 9a278c75c918..a41a92fb8d48 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
 	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
 
 	/* Core Clock Outputs */
+	DEF_FIXED("z2",        R8A77990_CLK_Z2,    CLK_PLL0D4,     1, 1),
 	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
 	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
 	DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
-- 
2.11.0

Re: [PATCH] clk: renesas: r8a77990: Add Z2 clock

[Geert Uytterhoeven]

Hi Simon,

On Mon, Jan 28, 2019 at 3:01 PM Simon Horman <horms+renesas@verge.net.au> wrote:
> Adds Z2 clock to CPG driver for the R-Car E3 (r8a77990) SoC.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
>         DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
>
>         /* Core Clock Outputs */
> +       DEF_FIXED("z2",        R8A77990_CLK_Z2,    CLK_PLL0D4,     1, 1),

According to R-Car Gen3 Hardware User's Manual rev. 1.50, the SYS-CPU
Divider 2 is controlled through the Z2FC bit field in the Frequency
Control Register C. So it is not a fixed clock, unlike on R-Car D3.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH] clk: renesas: r8a77990: Add Z2 clock

[Simon Horman]

On Mon, Jan 28, 2019 at 04:12:03PM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Mon, Jan 28, 2019 at 3:01 PM Simon Horman <horms+renesas@verge.net.au> wrote:
> > Adds Z2 clock to CPG driver for the R-Car E3 (r8a77990) SoC.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
> > @@ -79,6 +79,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
> >         DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
> >
> >         /* Core Clock Outputs */
> > +       DEF_FIXED("z2",        R8A77990_CLK_Z2,    CLK_PLL0D4,     1, 1),
> 
> According to R-Car Gen3 Hardware User's Manual rev. 1.50, the SYS-CPU
> Divider 2 is controlled through the Z2FC bit field in the Frequency
> Control Register C. So it is not a fixed clock, unlike on R-Car D3.

Thanks, I will look into that.