* [PATCH v4 01/10] dt-bindings: usb: generic-ohci: Document dr_mode property
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 02/10] dt-bindings: usb: generic-ehci: " Biju Das
` (8 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, linux-usb, devicetree,
Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes the dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v3->v4:
* Added Rob's Acked-by tag.
v2->v3:
* Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
v2:
* New patch
---
Documentation/devicetree/bindings/usb/generic-ohci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
index 0f5f6ea702d0..569777a76c90 100644
--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
@@ -109,6 +109,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 02/10] dt-bindings: usb: generic-ehci: Document dr_mode property
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
2021-07-19 12:19 ` [PATCH v4 01/10] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
` (7 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, linux-usb, devicetree,
Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document the optional property dr_mode present on both RZ/G2 and
R-Car Gen3 SoCs.
It fixes dtbs_check warning,
'dr_mode' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v3->v4:
* Added Rob's Acked-by tag.
v2->v3:
* Dropped RZ/G2L SoC and USBPHY control IP is modelled as reset binding.
v2:
* New patch
---
Documentation/devicetree/bindings/usb/generic-ehci.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index 8089dc956ba3..f6e5e4abb85b 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -142,6 +142,11 @@ properties:
iommus:
maxItems: 1
+ dr_mode:
+ enum:
+ - host
+ - otg
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
2021-07-19 12:19 ` [PATCH v4 01/10] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
2021-07-19 12:19 ` [PATCH v4 02/10] dt-bindings: usb: generic-ehci: " Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 15:27 ` Rob Herring
2021-07-26 22:26 ` Rob Herring
2021-07-19 12:19 ` [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver Biju Das
` (6 subsequent siblings)
9 siblings, 2 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring
Cc: Biju Das, devicetree, Geert Uytterhoeven, Yoshihiro Shimoda,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Add device tree binding document for RZ/G2L USBPHY Control Device.
It mainly controls reset and power down of the USB/PHY.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
v3->v4:
* Dropped reset reference.
* Added Rb-tag from Rob.
v3:
* New patch.
* Modelled USBPHY control from phy bindings to reset bindings, since the
IP mainly contols the reset of USB PHY.
---
.../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 000000000000..b13514e6783d
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USBPHY Control
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+ The RZ/G2L USBPHY Control mainly controls reset and power down of the
+ USB/PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usbphy-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+ description: |
+ The phandle's argument in the reset specifier is the PHY reset associated
+ with the USB port.
+ 0 = Port 1 Phy reset
+ 1 = Port 2 Phy reset
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - power-domains
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0x11c40000 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (2 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-27 7:55 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 05/10] arm64: configs: defconfig: Enable RZ/G2L USBPHY " Biju Das
` (5 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Philipp Zabel
Cc: Biju Das, Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Add support for RZ/G2L USBPHY Control driver. It mainly controls
reset and power down of the USB/PHY.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* Incorporated the changes suggested by Philipp
* removed *dev pointer, replaced the magic number 0xff
* started using of_reset_simple_xlate
* Added spinlock for read-modify-writes
v3:
* New driver. As per Rob's suggestion, Modelled IP as a reset driver,
since it mainly controls reset and power down of the PHY.
---
drivers/reset/Kconfig | 7 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-rzg2l-usbphy-ctrl.c | 175 ++++++++++++++++++++++++
3 files changed, 183 insertions(+)
create mode 100644 drivers/reset/reset-rzg2l-usbphy-ctrl.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 328f70f633eb..ed65ea66987b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -181,6 +181,13 @@ config RESET_RASPBERRYPI
interfacing with RPi4's co-processor and model these firmware
initialization routines as reset lines.
+config RESET_RZG2L_USBPHY_CTRL
+ tristate "Renesas RZ/G2L USBPHY control driver"
+ depends on ARCH_R9A07G044 || COMPILE_TEST
+ help
+ Support for USBPHY Control found on RZ/G2L family. It mainly
+ controls reset and power down of the USB/PHY.
+
config RESET_SCMI
tristate "Reset driver controlled via ARM SCMI interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index ea8b8d9ca565..21d46d8869ff 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
+obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
new file mode 100644
index 000000000000..e0704fd2b533
--- /dev/null
+++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L USBPHY control driver
+ *
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/reset-controller.h>
+
+#define RESET 0x000
+
+#define RESET_SEL_PLLRESET BIT(12)
+#define RESET_PLLRESET BIT(8)
+
+#define RESET_SEL_P2RESET BIT(5)
+#define RESET_SEL_P1RESET BIT(4)
+#define RESET_PHYRST_2 BIT(1)
+#define RESET_PHYRST_1 BIT(0)
+
+#define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2)
+#define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1)
+
+#define NUM_PORTS 2
+
+struct rzg2l_usbphy_ctrl_priv {
+ struct reset_controller_dev rcdev;
+ struct reset_control *rstc;
+ void __iomem *base;
+
+ spinlock_t lock;
+};
+
+#define rcdev_to_priv(x) container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev)
+
+static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
+ void __iomem *base = priv->base;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(base + RESET);
+ val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
+ if (port_mask == (val & port_mask))
+ val |= RESET_PLLRESET;
+ writel(val, base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ void __iomem *base = priv->base;
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(base + RESET);
+
+ val |= RESET_SEL_PLLRESET;
+ val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
+ writel(val, base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
+ u32 port_mask;
+
+ port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
+
+ return !!(readl(priv->base + RESET) & port_mask);
+}
+
+static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
+ { .compatible = "renesas,rzg2l-usbphy-ctrl" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
+
+static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
+ .assert = rzg2l_usbphy_ctrl_assert,
+ .deassert = rzg2l_usbphy_ctrl_deassert,
+ .status = rzg2l_usbphy_ctrl_status,
+};
+
+static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rzg2l_usbphy_ctrl_priv *priv;
+ unsigned long flags;
+ int error;
+ u32 val;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(priv->rstc))
+ return dev_err_probe(dev, PTR_ERR(priv->rstc),
+ "failed to get reset\n");
+
+ reset_control_deassert(priv->rstc);
+
+ priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.nr_resets = NUM_PORTS;
+ priv->rcdev.of_node = dev->of_node;
+ priv->rcdev.dev = dev;
+
+ error = devm_reset_controller_register(dev, &priv->rcdev);
+ if (error)
+ return error;
+
+ spin_lock_init(&priv->lock);
+ dev_set_drvdata(dev, priv);
+
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_resume_and_get(&pdev->dev);
+
+ /* put pll and phy into reset state */
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(priv->base + RESET);
+ val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
+ writel(val, priv->base + RESET);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return 0;
+}
+
+static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
+{
+ struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(priv->rstc);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_usbphy_ctrl_driver = {
+ .driver = {
+ .name = "rzg2l_usbphy_ctrl",
+ .of_match_table = rzg2l_usbphy_ctrl_match_table,
+ },
+ .probe = rzg2l_usbphy_ctrl_probe,
+ .remove = rzg2l_usbphy_ctrl_remove,
+};
+module_platform_driver(rzg2l_usbphy_ctrl_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
+MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 05/10] arm64: configs: defconfig: Enable RZ/G2L USBPHY control driver
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (3 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
` (4 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Biju Das, Shawn Guo, Bjorn Andersson, Krzysztof Kozlowski,
Guido Günther, Vinod Koul, Michael Walle, Dmitry Baryshkov,
Enric Balletbo i Serra, Nishanth Menon, Douglas Anderson,
Lad Prabhakar, Anson Huang, linux-arm-kernel, Geert Uytterhoeven,
Chris Paterson, Biju Das, linux-renesas-soc
RZ/G2L SoC supports USBPHY control,so enable it in ARM64 defconfig.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* No Change.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e77a2ed23910..cb2a0082b12c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1100,6 +1100,7 @@ CONFIG_PWM_VISCONTI=m
CONFIG_SL28CPLD_INTC=y
CONFIG_QCOM_PDC=y
CONFIG_RESET_IMX7=y
+CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_QCOM_AOSS=y
CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_TI_SCI=y
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (4 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 05/10] arm64: configs: defconfig: Enable RZ/G2L USBPHY " Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-26 22:28 ` Rob Herring
2021-07-19 12:19 ` [PATCH v4 07/10] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L Biju Das
` (3 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda,
linux-phy, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Document USB phy bindings for RZ/G2L SoC.
RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
a different OTG-BC interrupt bit for device recognition. Apart from this,
the PHY reset is controlled by USBPHY control IP and Document reset is a
required property.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* Removed second reset
* Added family specific compatible string.
v2->v3
* Created a new compatible for RZ/G2L as per Geert's suggestion.
* Added resets required properties for RZ/G2L SoC.
---
.../bindings/phy/renesas,usb2-phy.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index d5dc5a3cdceb..151158d7a224 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -30,6 +30,11 @@ properties:
- renesas,usb2-phy-r8a77995 # R-Car D3
- const: renesas,rcar-gen3-usb2-phy
+ - items:
+ - enum:
+ - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
+ - const: renesas,rzg2l-usb2-phy # RZ/G2L family
+
reg:
maxItems: 1
@@ -91,6 +96,20 @@ required:
- clocks
- '#phy-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2l-usb2-phy
+ then:
+ properties:
+ resets:
+ description: |
+ USB/PHY reset associated with the port.
+ required:
+ - resets
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 07/10] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (5 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 08/10] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
` (2 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Biju Das, Kishon Vijay Abraham I, Vinod Koul, linux-renesas-soc,
linux-phy, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
This patch adds OTG support for RZ/G2L SoC.
We need to use a different compatible string due to some differences
with R-Car Gen3 USB2.0 PHY. It uses line ctrl register for OTG_ID
pin changes and different OTG-BC interrupt bit for device recognition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4;
* using family compatible instead of SoC specific.
v3:
* Made seperate compatible for RZ/G2L.
* Extended rcar_gen3_phy_usb2_match_table[].data to support RZ/G2L.
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 97 ++++++++++++++++++------
1 file changed, 73 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index fbc55232120e..9de617ca9daa 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -64,6 +64,7 @@
/* VBCTRL */
#define USB2_VBCTRL_OCCLREN BIT(16)
#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
+#define USB2_VBCTRL_VBOUT BIT(0)
/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN BIT(19)
@@ -78,6 +79,10 @@
#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS BIT(4)
+/* RZ/G2L specific */
+#define USB2_OBINT_IDCHG_EN BIT(0)
+#define USB2_LINECTRL1_USB2_IDMON BIT(0)
+
#define NUM_OF_PHYS 4
enum rcar_gen3_phy_index {
PHY_INDEX_BOTH_HC,
@@ -112,9 +117,16 @@ struct rcar_gen3_chan {
struct mutex lock; /* protects rphys[...].powered */
enum usb_dr_mode dr_mode;
int irq;
+ u32 obint_enable_bits;
bool extcon_host;
bool is_otg_channel;
bool uses_otg_pins;
+ bool soc_no_adp_ctrl;
+};
+
+struct rcar_gen3_phy_drv_data {
+ const struct phy_ops *phy_usb2_ops;
+ bool no_adp_ctrl;
};
/*
@@ -172,14 +184,22 @@ static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
void __iomem *usb2_base = ch->base;
- u32 val = readl(usb2_base + USB2_ADPCTRL);
+ u32 vbus_ctrl_reg = USB2_ADPCTRL;
+ u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
+ u32 val;
dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
+ if (ch->soc_no_adp_ctrl) {
+ vbus_ctrl_reg = USB2_VBCTRL;
+ vbus_ctrl_val = USB2_VBCTRL_VBOUT;
+ }
+
+ val = readl(usb2_base + vbus_ctrl_reg);
if (vbus)
- val |= USB2_ADPCTRL_DRVVBUS;
+ val |= vbus_ctrl_val;
else
- val &= ~USB2_ADPCTRL_DRVVBUS;
- writel(val, usb2_base + USB2_ADPCTRL);
+ val &= ~vbus_ctrl_val;
+ writel(val, usb2_base + vbus_ctrl_reg);
}
static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
@@ -188,9 +208,9 @@ static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
u32 val = readl(usb2_base + USB2_OBINTEN);
if (ch->uses_otg_pins && enable)
- val |= USB2_OBINT_BITS;
+ val |= ch->obint_enable_bits;
else
- val &= ~USB2_OBINT_BITS;
+ val &= ~ch->obint_enable_bits;
writel(val, usb2_base + USB2_OBINTEN);
}
@@ -252,6 +272,9 @@ static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
if (!ch->uses_otg_pins)
return (ch->dr_mode == USB_DR_MODE_HOST) ? false : true;
+ if (ch->soc_no_adp_ctrl)
+ return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
+
return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}
@@ -376,16 +399,17 @@ static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
writel(val, usb2_base + USB2_LINECTRL1);
- val = readl(usb2_base + USB2_VBCTRL);
- val &= ~USB2_VBCTRL_OCCLREN;
- writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
- val = readl(usb2_base + USB2_ADPCTRL);
- writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
-
+ if (!ch->soc_no_adp_ctrl) {
+ val = readl(usb2_base + USB2_VBCTRL);
+ val &= ~USB2_VBCTRL_OCCLREN;
+ writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
+ val = readl(usb2_base + USB2_ADPCTRL);
+ writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
+ }
msleep(20);
writel(0xffffffff, usb2_base + USB2_OBINTSTA);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTEN);
rcar_gen3_device_recognition(ch);
}
@@ -397,9 +421,9 @@ static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
u32 status = readl(usb2_base + USB2_OBINTSTA);
irqreturn_t ret = IRQ_NONE;
- if (status & USB2_OBINT_BITS) {
+ if (status & ch->obint_enable_bits) {
dev_vdbg(ch->dev, "%s: %08x\n", __func__, status);
- writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
+ writel(ch->obint_enable_bits, usb2_base + USB2_OBINTSTA);
rcar_gen3_device_recognition(ch);
ret = IRQ_HANDLED;
}
@@ -535,26 +559,45 @@ static const struct phy_ops rz_g1c_phy_usb2_ops = {
.owner = THIS_MODULE,
};
+static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
+ .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+ .no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
+ .phy_usb2_ops = &rz_g1c_phy_usb2_ops,
+ .no_adp_ctrl = false,
+};
+
+static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
+ .phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
+ .no_adp_ctrl = true,
+};
+
static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
{
.compatible = "renesas,usb2-phy-r8a77470",
- .data = &rz_g1c_phy_usb2_ops,
+ .data = &rz_g1c_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a7795",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a7796",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{
.compatible = "renesas,usb2-phy-r8a77965",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
+ },
+ {
+ .compatible = "renesas,rzg2l-usb2-phy",
+ .data = &rz_g2l_phy_usb2_data,
},
{
.compatible = "renesas,rcar-gen3-usb2-phy",
- .data = &rcar_gen3_phy_usb2_ops,
+ .data = &rcar_gen3_phy_usb2_data,
},
{ /* sentinel */ },
};
@@ -608,10 +651,10 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
{
+ const struct rcar_gen3_phy_drv_data *phy_data;
struct device *dev = &pdev->dev;
struct rcar_gen3_chan *channel;
struct phy_provider *provider;
- const struct phy_ops *phy_usb2_ops;
int ret = 0, i;
if (!dev->of_node) {
@@ -627,6 +670,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
if (IS_ERR(channel->base))
return PTR_ERR(channel->base);
+ channel->obint_enable_bits = USB2_OBINT_BITS;
/* get irq number here and request_irq for OTG in phy_init */
channel->irq = platform_get_irq_optional(pdev, 0);
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
@@ -653,16 +697,21 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
* And then, phy-core will manage runtime pm for this device.
*/
pm_runtime_enable(dev);
- phy_usb2_ops = of_device_get_match_data(dev);
- if (!phy_usb2_ops) {
+
+ phy_data = of_device_get_match_data(dev);
+ if (!phy_data) {
ret = -EINVAL;
goto error;
}
+ channel->soc_no_adp_ctrl = phy_data->no_adp_ctrl;
+ if (phy_data->no_adp_ctrl)
+ channel->obint_enable_bits = USB2_OBINT_IDCHG_EN;
+
mutex_init(&channel->lock);
for (i = 0; i < NUM_OF_PHYS; i++) {
channel->rphys[i].phy = devm_phy_create(dev, NULL,
- phy_usb2_ops);
+ phy_data->phy_usb2_ops);
if (IS_ERR(channel->rphys[i].phy)) {
dev_err(dev, "Failed to create USB2 PHY\n");
ret = PTR_ERR(channel->rphys[i].phy);
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 08/10] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (6 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 07/10] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-07-19 12:19 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 phy and host support to SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V3->v4:
* Removed second reset from phy node.
V3:
* Added reset entries
* Updated compatible, phy and reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 94 ++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index cdc1da1ede9c..24910ecc683c 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -236,6 +236,100 @@
<0x0 0x11940000 0 0x60000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+
+ phyrst: usbphy-ctrl@11c40000 {
+ compatible = "renesas,r9a07g044-usbphy-ctrl",
+ "renesas,rzg2l-usbphy-ctrl";
+ reg = <0 0x11c40000 0 0x10000>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+ resets = <&cpg R9A07G044_USB_PRESETN>;
+ power-domains = <&cpg>;
+ #reset-cells = <1>;
+ };
+
+ ohci0: usb@11c50000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c50000 0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ohci1: usb@11c70000 {
+ compatible = "generic-ohci";
+ reg = <0 0x11c70000 0 0x100>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 1>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci0: usb@11c50100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c50100 0 0x100>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2H0_HRESETN>;
+ phys = <&usb2_phy0 2>;
+ phy-names = "usb";
+ companion = <&ohci0>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ehci1: usb@11c70100 {
+ compatible = "generic-ehci";
+ reg = <0 0x11c70100 0 0x100>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>,
+ <&cpg R9A07G044_USB_U2H1_HRESETN>;
+ phys = <&usb2_phy1 2>;
+ phy-names = "usb";
+ companion = <&ohci1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c50200 0 0x700>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
+ resets = <&phyrst 0>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ compatible = "renesas,usb2-phy-r9a07g044",
+ "renesas,rzg2l-usb2-phy";
+ reg = <0 0x11c70200 0 0x700>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
+ resets = <&phyrst 1>;
+ #phy-cells = <1>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (7 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 08/10] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
@ 2021-07-19 12:19 ` Biju Das
2021-07-26 22:30 ` Rob Herring
2021-07-19 12:19 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
9 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Document RZ/G2L (R9A07G044L) SoC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* Added maxitems in interrupt property as per Rob's suggestion.
v3:
* Updated the bindings as per the USBPHY control IP.
---
.../bindings/usb/renesas,usbhs.yaml | 22 +++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index ad73339ffe1d..a85ad392d443 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -17,7 +17,9 @@ properties:
- const: renesas,rza1-usbhs
- items:
- - const: renesas,usbhs-r7s9210 # RZ/A2
+ - enum:
+ - renesas,usbhs-r7s9210 # RZ/A2
+ - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
- const: renesas,rza2-usbhs
- items:
@@ -59,7 +61,8 @@ properties:
- description: USB 2.0 clock selector
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 4
renesas,buswait:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -108,6 +111,21 @@ required:
- clocks
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,usbhs-r9a07g044
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: U2P_IXL_INT
+ - description: U2P_INT_DMA[0]
+ - description: U2P_INT_DMA[1]
+ - description: U2P_INT_DMAERR
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add USB2.0 device support
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
` (8 preceding siblings ...)
2021-07-19 12:19 ` [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-07-19 12:19 ` Biju Das
9 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-19 12:19 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add USB2.0 device support to RZ/G2L SoC DT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
* No change.
V3:
* Updated reset entries.
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 24910ecc683c..d846469ded7f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -330,6 +330,25 @@
power-domains = <&cpg>;
status = "disabled";
};
+
+ hsusb: usb@11c60000 {
+ compatible = "renesas,usbhs-r9a07g044",
+ "renesas,rza2-usbhs";
+ reg = <0 0x11c60000 0 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
+ <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
+ resets = <&phyrst 0>,
+ <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
+ renesas,buswait = <7>;
+ phys = <&usb2_phy0 3>;
+ phy-names = "usb";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
};
timer {
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-19 12:19 ` [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
@ 2021-07-19 15:27 ` Rob Herring
2021-07-20 11:26 ` Biju Das
2021-07-26 22:26 ` Rob Herring
1 sibling, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-07-19 15:27 UTC (permalink / raw)
To: Biju Das
Cc: Chris Paterson, Biju Das, Yoshihiro Shimoda,
Prabhakar Mahadev Lad, Geert Uytterhoeven, Rob Herring,
Philipp Zabel, linux-renesas-soc, devicetree
On Mon, 19 Jul 2021 13:19:31 +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v3->v4:
> * Dropped reset reference.
> * Added Rb-tag from Rob.
> v3:
> * New patch.
> * Modelled USBPHY control from phy bindings to reset bindings, since the
> IP mainly contols the reset of USB PHY.
> ---
> .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dts:25.30-31 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1418: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1506961
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-19 15:27 ` Rob Herring
@ 2021-07-20 11:26 ` Biju Das
2021-07-20 16:36 ` Rob Herring
0 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-20 11:26 UTC (permalink / raw)
To: Rob Herring
Cc: Chris Paterson, Biju Das, Yoshihiro Shimoda,
Prabhakar Mahadev Lad, Geert Uytterhoeven, Rob Herring,
Philipp Zabel, linux-renesas-soc, devicetree
Hi Rob,
> Subject: Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY
> Control bindings
>
> On Mon, 19 Jul 2021 13:19:31 +0100, Biju Das wrote:
> > Add device tree binding document for RZ/G2L USBPHY Control Device.
> > It mainly controls reset and power down of the USB/PHY.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > ---
> > v3->v4:
> > * Dropped reset reference.
> > * Added Rb-tag from Rob.
> > v3:
> > * New patch.
> > * Modelled USBPHY control from phy bindings to reset bindings, since
> the
> > IP mainly contols the reset of USB PHY.
> > ---
> > .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
> > 1 file changed, 65 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Error: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> ctrl.example.dts:25.30-31 syntax error FATAL ERROR: Unable to parse input
> tree
> make[1]: *** [scripts/Makefile.lib:380:
> Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> ctrl.example.dt.yaml] Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1418: dt_binding_check] Error 2 \ndoc reference errors
> (make refcheckdocs):
>
> See
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fpatch%2F1506961&data=04%7C01%7Cbiju.das.jz%40bp.renesas
> .com%7Cb02057306f9b4db2426008d94ac9ce37%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C637623052878040806%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=N4%2F9GofL
> NWbtPDddI38ActeGRqtfxdNANC4T241Or1M%3D&reserved=0
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
The dependency patch for the bot error is present on 5.14-rc2 but not on 5.14-rc1.
Regards,
Biju
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-20 11:26 ` Biju Das
@ 2021-07-20 16:36 ` Rob Herring
2021-07-20 16:56 ` Biju Das
0 siblings, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-07-20 16:36 UTC (permalink / raw)
To: Biju Das
Cc: Chris Paterson, Biju Das, Yoshihiro Shimoda,
Prabhakar Mahadev Lad, Geert Uytterhoeven, Philipp Zabel,
linux-renesas-soc, devicetree
On Tue, Jul 20, 2021 at 5:26 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Rob,
>
> > Subject: Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY
> > Control bindings
> >
> > On Mon, 19 Jul 2021 13:19:31 +0100, Biju Das wrote:
> > > Add device tree binding document for RZ/G2L USBPHY Control Device.
> > > It mainly controls reset and power down of the USB/PHY.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > ---
> > > v3->v4:
> > > * Dropped reset reference.
> > > * Added Rb-tag from Rob.
> > > v3:
> > > * New patch.
> > > * Modelled USBPHY control from phy bindings to reset bindings, since
> > the
> > > IP mainly contols the reset of USB PHY.
> > > ---
> > > .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> > >
> >
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> >
> > yamllint warnings/errors:
> >
> > dtschema/dtc warnings/errors:
> > Error: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> > ctrl.example.dts:25.30-31 syntax error FATAL ERROR: Unable to parse input
> > tree
> > make[1]: *** [scripts/Makefile.lib:380:
> > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> > ctrl.example.dt.yaml] Error 1
> > make[1]: *** Waiting for unfinished jobs....
> > make: *** [Makefile:1418: dt_binding_check] Error 2 \ndoc reference errors
> > (make refcheckdocs):
> >
> > See
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> > k.ozlabs.org%2Fpatch%2F1506961&data=04%7C01%7Cbiju.das.jz%40bp.renesas
> > .com%7Cb02057306f9b4db2426008d94ac9ce37%7C53d82571da1947e49cb4625a166a4a2a
> > %7C0%7C0%7C637623052878040806%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> > LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=N4%2F9GofL
> > NWbtPDddI38ActeGRqtfxdNANC4T241Or1M%3D&reserved=0
> >
> > This check can fail if there are any dependencies. The base for a patch
> > series is generally the most recent rc1.
>
> The dependency patch for the bot error is present on 5.14-rc2 but not on 5.14-rc1.
Ok, I've updated the base to rc2. Please note a dependency like that
(anything that's not the last rc1) next time.
Rob
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-20 16:36 ` Rob Herring
@ 2021-07-20 16:56 ` Biju Das
0 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-20 16:56 UTC (permalink / raw)
To: Rob Herring
Cc: Chris Paterson, Biju Das, Yoshihiro Shimoda,
Prabhakar Mahadev Lad, Geert Uytterhoeven, Philipp Zabel,
linux-renesas-soc, devicetree
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY
> Control bindings
>
> On Tue, Jul 20, 2021 at 5:26 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Rob,
> >
> > > Subject: Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L
> > > USBPHY Control bindings
> > >
> > > On Mon, 19 Jul 2021 13:19:31 +0100, Biju Das wrote:
> > > > Add device tree binding document for RZ/G2L USBPHY Control Device.
> > > > It mainly controls reset and power down of the USB/PHY.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > ---
> > > > v3->v4:
> > > > * Dropped reset reference.
> > > > * Added Rb-tag from Rob.
> > > > v3:
> > > > * New patch.
> > > > * Modelled USBPHY control from phy bindings to reset bindings,
> > > > since
> > > the
> > > > IP mainly contols the reset of USB PHY.
> > > > ---
> > > > .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65
> +++++++++++++++++++
> > > > 1 file changed, 65 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.
> > > > yaml
> > > >
> > >
> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m
> dt_binding_check'
> > > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > >
> > > yamllint warnings/errors:
> > >
> > > dtschema/dtc warnings/errors:
> > > Error: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> > > ctrl.example.dts:25.30-31 syntax error FATAL ERROR: Unable to parse
> > > input tree
> > > make[1]: *** [scripts/Makefile.lib:380:
> > > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-
> > > ctrl.example.dt.yaml] Error 1
> > > make[1]: *** Waiting for unfinished jobs....
> > > make: *** [Makefile:1418: dt_binding_check] Error 2 \ndoc reference
> > > errors (make refcheckdocs):
> > >
> > > See
> > > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa
> > > tchwor
> > > k.ozlabs.org%2Fpatch%2F1506961&data=04%7C01%7Cbiju.das.jz%40bp.r
> > > enesas
> > > .com%7Cb02057306f9b4db2426008d94ac9ce37%7C53d82571da1947e49cb4625a16
> > > 6a4a2a
> > > %7C0%7C0%7C637623052878040806%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> > > AwMDAi
> > > LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=N4%2
> > > F9GofL
> > > NWbtPDddI38ActeGRqtfxdNANC4T241Or1M%3D&reserved=0
> > >
> > > This check can fail if there are any dependencies. The base for a
> > > patch series is generally the most recent rc1.
> >
> > The dependency patch for the bot error is present on 5.14-rc2 but not on
> 5.14-rc1.
>
> Ok, I've updated the base to rc2. Please note a dependency like that
> (anything that's not the last rc1) next time.
Agreed. Do I need to resend the current binding patch? Please let me know.
Regards,
Biju
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings
2021-07-19 12:19 ` [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
2021-07-19 15:27 ` Rob Herring
@ 2021-07-26 22:26 ` Rob Herring
1 sibling, 0 replies; 23+ messages in thread
From: Rob Herring @ 2021-07-26 22:26 UTC (permalink / raw)
To: Biju Das
Cc: Philipp Zabel, devicetree, Geert Uytterhoeven, Yoshihiro Shimoda,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Mon, Jul 19, 2021 at 01:19:31PM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> v3->v4:
> * Dropped reset reference.
> * Added Rb-tag from Rob.
> v3:
> * New patch.
> * Modelled USBPHY control from phy bindings to reset bindings, since the
> IP mainly contols the reset of USB PHY.
> ---
> .../reset/renesas,rzg2l-usbphy-ctrl.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-19 12:19 ` [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
@ 2021-07-26 22:28 ` Rob Herring
2021-07-27 14:58 ` Biju Das
0 siblings, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-07-26 22:28 UTC (permalink / raw)
To: Biju Das
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, Jul 19, 2021 at 01:19:34PM +0100, Biju Das wrote:
> Document USB phy bindings for RZ/G2L SoC.
>
> RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It uses
> a different OTG-BC interrupt bit for device recognition. Apart from this,
> the PHY reset is controlled by USBPHY control IP and Document reset is a
> required property.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3->v4:
> * Removed second reset
> * Added family specific compatible string.
> v2->v3
> * Created a new compatible for RZ/G2L as per Geert's suggestion.
> * Added resets required properties for RZ/G2L SoC.
> ---
> .../bindings/phy/renesas,usb2-phy.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> index d5dc5a3cdceb..151158d7a224 100644
> --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> @@ -30,6 +30,11 @@ properties:
> - renesas,usb2-phy-r8a77995 # R-Car D3
> - const: renesas,rcar-gen3-usb2-phy
>
> + - items:
> + - enum:
> + - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> + - const: renesas,rzg2l-usb2-phy # RZ/G2L family
> +
> reg:
> maxItems: 1
>
> @@ -91,6 +96,20 @@ required:
> - clocks
> - '#phy-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,rzg2l-usb2-phy
> + then:
> + properties:
> + resets:
> + description: |
> + USB/PHY reset associated with the port.
You don't need 'properties' part here. Just 'required'.
> + required:
> + - resets
> +
> additionalProperties: false
>
> examples:
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-07-19 12:19 ` [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
@ 2021-07-26 22:30 ` Rob Herring
2021-07-27 14:59 ` Biju Das
0 siblings, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-07-26 22:30 UTC (permalink / raw)
To: Biju Das
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
On Mon, Jul 19, 2021 at 01:19:37PM +0100, Biju Das wrote:
> Document RZ/G2L (R9A07G044L) SoC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3->v4:
> * Added maxitems in interrupt property as per Rob's suggestion.
> v3:
> * Updated the bindings as per the USBPHY control IP.
> ---
> .../bindings/usb/renesas,usbhs.yaml | 22 +++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> index ad73339ffe1d..a85ad392d443 100644
> --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> @@ -17,7 +17,9 @@ properties:
> - const: renesas,rza1-usbhs
>
> - items:
> - - const: renesas,usbhs-r7s9210 # RZ/A2
> + - enum:
> + - renesas,usbhs-r7s9210 # RZ/A2
> + - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
> - const: renesas,rza2-usbhs
>
> - items:
> @@ -59,7 +61,8 @@ properties:
> - description: USB 2.0 clock selector
>
> interrupts:
> - maxItems: 1
> + minItems: 1
> + maxItems: 4
>
> renesas,buswait:
> $ref: /schemas/types.yaml#/definitions/uint32
> @@ -108,6 +111,21 @@ required:
> - clocks
> - interrupts
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,usbhs-r9a07g044
> + then:
> + properties:
> + interrupts:
> + items:
> + - description: U2P_IXL_INT
> + - description: U2P_INT_DMA[0]
> + - description: U2P_INT_DMA[1]
> + - description: U2P_INT_DMAERR
else:
properties:
interrupts:
maxItems: 1
> +
> additionalProperties: false
>
> examples:
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
2021-07-19 12:19 ` [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver Biju Das
@ 2021-07-27 7:55 ` Biju Das
2021-07-27 13:37 ` Philipp Zabel
0 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-27 7:55 UTC (permalink / raw)
To: Biju Das, Philipp Zabel
Cc: Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi All,
Gentle ping. Are we happy with this patch? Please let me know.
Regards,
Biju
> Subject: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
>
> Add support for RZ/G2L USBPHY Control driver. It mainly controls reset and
> power down of the USB/PHY.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3->v4:
> * Incorporated the changes suggested by Philipp
> * removed *dev pointer, replaced the magic number 0xff
> * started using of_reset_simple_xlate
> * Added spinlock for read-modify-writes
> v3:
> * New driver. As per Rob's suggestion, Modelled IP as a reset driver,
> since it mainly controls reset and power down of the PHY.
> ---
> drivers/reset/Kconfig | 7 +
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-rzg2l-usbphy-ctrl.c | 175 ++++++++++++++++++++++++
> 3 files changed, 183 insertions(+)
> create mode 100644 drivers/reset/reset-rzg2l-usbphy-ctrl.c
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index
> 328f70f633eb..ed65ea66987b 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -181,6 +181,13 @@ config RESET_RASPBERRYPI
> interfacing with RPi4's co-processor and model these firmware
> initialization routines as reset lines.
>
> +config RESET_RZG2L_USBPHY_CTRL
> + tristate "Renesas RZ/G2L USBPHY control driver"
> + depends on ARCH_R9A07G044 || COMPILE_TEST
> + help
> + Support for USBPHY Control found on RZ/G2L family. It mainly
> + controls reset and power down of the USB/PHY.
> +
> config RESET_SCMI
> tristate "Reset driver controlled via ARM SCMI interface"
> depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git
> a/drivers/reset/Makefile b/drivers/reset/Makefile index
> ea8b8d9ca565..21d46d8869ff 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -25,6 +25,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
> obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
> obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
> obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
> +obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
> obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
> obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
> obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git
> a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-
> usbphy-ctrl.c
> new file mode 100644
> index 000000000000..e0704fd2b533
> --- /dev/null
> +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> @@ -0,0 +1,175 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/G2L USBPHY control driver
> + *
> + * Copyright (C) 2021 Renesas Electronics Corporation */
> +
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/reset-controller.h>
> +
> +#define RESET 0x000
> +
> +#define RESET_SEL_PLLRESET BIT(12)
> +#define RESET_PLLRESET BIT(8)
> +
> +#define RESET_SEL_P2RESET BIT(5)
> +#define RESET_SEL_P1RESET BIT(4)
> +#define RESET_PHYRST_2 BIT(1)
> +#define RESET_PHYRST_1 BIT(0)
> +
> +#define PHY_RESET_PORT2 (RESET_SEL_P2RESET | RESET_PHYRST_2)
> +#define PHY_RESET_PORT1 (RESET_SEL_P1RESET | RESET_PHYRST_1)
> +
> +#define NUM_PORTS 2
> +
> +struct rzg2l_usbphy_ctrl_priv {
> + struct reset_controller_dev rcdev;
> + struct reset_control *rstc;
> + void __iomem *base;
> +
> + spinlock_t lock;
> +};
> +
> +#define rcdev_to_priv(x) container_of(x, struct
> rzg2l_usbphy_ctrl_priv, rcdev)
> +
> +static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
> + u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
> + void __iomem *base = priv->base;
> + unsigned long flags;
> + u32 val;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + val = readl(base + RESET);
> + val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
> + if (port_mask == (val & port_mask))
> + val |= RESET_PLLRESET;
> + writel(val, base + RESET);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return 0;
> +}
> +
> +static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
> + void __iomem *base = priv->base;
> + unsigned long flags;
> + u32 val;
> +
> + spin_lock_irqsave(&priv->lock, flags);
> + val = readl(base + RESET);
> +
> + val |= RESET_SEL_PLLRESET;
> + val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
> + writel(val, base + RESET);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return 0;
> +}
> +
> +static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
> + u32 port_mask;
> +
> + port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
> +
> + return !!(readl(priv->base + RESET) & port_mask); }
> +
> +static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
> + { .compatible = "renesas,rzg2l-usbphy-ctrl" },
> + { /* Sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
> +
> +static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
> + .assert = rzg2l_usbphy_ctrl_assert,
> + .deassert = rzg2l_usbphy_ctrl_deassert,
> + .status = rzg2l_usbphy_ctrl_status,
> +};
> +
> +static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev) {
> + struct device *dev = &pdev->dev;
> + struct rzg2l_usbphy_ctrl_priv *priv;
> + unsigned long flags;
> + int error;
> + u32 val;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(priv->rstc))
> + return dev_err_probe(dev, PTR_ERR(priv->rstc),
> + "failed to get reset\n");
> +
> + reset_control_deassert(priv->rstc);
> +
> + priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
> + priv->rcdev.of_reset_n_cells = 1;
> + priv->rcdev.nr_resets = NUM_PORTS;
> + priv->rcdev.of_node = dev->of_node;
> + priv->rcdev.dev = dev;
> +
> + error = devm_reset_controller_register(dev, &priv->rcdev);
> + if (error)
> + return error;
> +
> + spin_lock_init(&priv->lock);
> + dev_set_drvdata(dev, priv);
> +
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_resume_and_get(&pdev->dev);
> +
> + /* put pll and phy into reset state */
> + spin_lock_irqsave(&priv->lock, flags);
> + val = readl(priv->base + RESET);
> + val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 |
> PHY_RESET_PORT1;
> + writel(val, priv->base + RESET);
> + spin_unlock_irqrestore(&priv->lock, flags);
> +
> + return 0;
> +}
> +
> +static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev) {
> + struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
> +
> + pm_runtime_put(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> + reset_control_assert(priv->rstc);
> +
> + return 0;
> +}
> +
> +static struct platform_driver rzg2l_usbphy_ctrl_driver = {
> + .driver = {
> + .name = "rzg2l_usbphy_ctrl",
> + .of_match_table = rzg2l_usbphy_ctrl_match_table,
> + },
> + .probe = rzg2l_usbphy_ctrl_probe,
> + .remove = rzg2l_usbphy_ctrl_remove,
> +};
> +module_platform_driver(rzg2l_usbphy_ctrl_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
> +MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");
> --
> 2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
2021-07-27 7:55 ` Biju Das
@ 2021-07-27 13:37 ` Philipp Zabel
2021-07-27 13:53 ` Biju Das
0 siblings, 1 reply; 23+ messages in thread
From: Philipp Zabel @ 2021-07-27 13:37 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Biju,
On Tue, 2021-07-27 at 07:55 +0000, Biju Das wrote:
> Hi All,
>
> Gentle ping. Are we happy with this patch? Please let me know.
Do you want me to pick up patches 3 and 4? Are there any dependencies
that I should be aware of?
regards
Philipp
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
2021-07-27 13:37 ` Philipp Zabel
@ 2021-07-27 13:53 ` Biju Das
2021-07-27 13:58 ` Philipp Zabel
0 siblings, 1 reply; 23+ messages in thread
From: Biju Das @ 2021-07-27 13:53 UTC (permalink / raw)
To: Philipp Zabel
Cc: Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Philipp,
Thanks for the feedback
> Subject: Re: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control
> driver
>
> Hi Biju,
>
> On Tue, 2021-07-27 at 07:55 +0000, Biju Das wrote:
> > Hi All,
> >
> > Gentle ping. Are we happy with this patch? Please let me know.
>
> Do you want me to pick up patches 3 and 4? Are there any dependencies that
> I should be aware of?
Yes please. There is no compile time dependency at all.
But there is a runtime dependency related to clock and the clock patches are queued for v5.15 on renesas-clk
And is present in Linux-next[1] as well.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20210726&id=03fa6e4b2622035389a4beb9699551d63d130493
Regards,
Biju
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver
2021-07-27 13:53 ` Biju Das
@ 2021-07-27 13:58 ` Philipp Zabel
0 siblings, 0 replies; 23+ messages in thread
From: Philipp Zabel @ 2021-07-27 13:58 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Yoshihiro Shimoda, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Biju,
On Tue, 2021-07-27 at 13:53 +0000, Biju Das wrote:
> Hi Philipp,
>
> Thanks for the feedback
>
> > Subject: Re: [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control
> > driver
> >
> > Hi Biju,
> >
> > On Tue, 2021-07-27 at 07:55 +0000, Biju Das wrote:
> > > Hi All,
> > >
> > > Gentle ping. Are we happy with this patch? Please let me know.
> >
> > Do you want me to pick up patches 3 and 4? Are there any dependencies that
> > I should be aware of?
>
> Yes please. There is no compile time dependency at all.
Applied to reset/next, thanks.
regards
Philipp
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings
2021-07-26 22:28 ` Rob Herring
@ 2021-07-27 14:58 ` Biju Das
0 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-27 14:58 UTC (permalink / raw)
To: Rob Herring
Cc: Kishon Vijay Abraham I, Vinod Koul, Yoshihiro Shimoda, linux-phy,
devicetree, Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document
> RZ/G2L phy bindings
>
> On Mon, Jul 19, 2021 at 01:19:34PM +0100, Biju Das wrote:
> > Document USB phy bindings for RZ/G2L SoC.
> >
> > RZ/G2L USB2.0 phy uses line ctrl register for OTG_ID pin changes. It
> > uses a different OTG-BC interrupt bit for device recognition. Apart
> > from this, the PHY reset is controlled by USBPHY control IP and
> > Document reset is a required property.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3->v4:
> > * Removed second reset
> > * Added family specific compatible string.
> > v2->v3
> > * Created a new compatible for RZ/G2L as per Geert's suggestion.
> > * Added resets required properties for RZ/G2L SoC.
> > ---
> > .../bindings/phy/renesas,usb2-phy.yaml | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > index d5dc5a3cdceb..151158d7a224 100644
> > --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> > @@ -30,6 +30,11 @@ properties:
> > - renesas,usb2-phy-r8a77995 # R-Car D3
> > - const: renesas,rcar-gen3-usb2-phy
> >
> > + - items:
> > + - enum:
> > + - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
> > + - const: renesas,rzg2l-usb2-phy # RZ/G2L family
> > +
> > reg:
> > maxItems: 1
> >
> > @@ -91,6 +96,20 @@ required:
> > - clocks
> > - '#phy-cells'
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,rzg2l-usb2-phy
> > + then:
> > + properties:
> > + resets:
> > + description: |
> > + USB/PHY reset associated with the port.
>
> You don't need 'properties' part here. Just 'required'.
OK. Will fix this in next version.
Regards,
Biju
>
> > + required:
> > + - resets
> > +
> > additionalProperties: false
> >
> > examples:
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 23+ messages in thread
* RE: [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings
2021-07-26 22:30 ` Rob Herring
@ 2021-07-27 14:59 ` Biju Das
0 siblings, 0 replies; 23+ messages in thread
From: Biju Das @ 2021-07-27 14:59 UTC (permalink / raw)
To: Rob Herring
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, linux-usb, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document
> RZ/G2L bindings
>
> On Mon, Jul 19, 2021 at 01:19:37PM +0100, Biju Das wrote:
> > Document RZ/G2L (R9A07G044L) SoC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3->v4:
> > * Added maxitems in interrupt property as per Rob's suggestion.
> > v3:
> > * Updated the bindings as per the USBPHY control IP.
> > ---
> > .../bindings/usb/renesas,usbhs.yaml | 22 +++++++++++++++++--
> > 1 file changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > index ad73339ffe1d..a85ad392d443 100644
> > --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > @@ -17,7 +17,9 @@ properties:
> > - const: renesas,rza1-usbhs
> >
> > - items:
> > - - const: renesas,usbhs-r7s9210 # RZ/A2
> > + - enum:
> > + - renesas,usbhs-r7s9210 # RZ/A2
> > + - renesas,usbhs-r9a07g044 # RZ/G2{L,LC}
> > - const: renesas,rza2-usbhs
> >
> > - items:
> > @@ -59,7 +61,8 @@ properties:
> > - description: USB 2.0 clock selector
> >
> > interrupts:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 4
> >
> > renesas,buswait:
> > $ref: /schemas/types.yaml#/definitions/uint32
> > @@ -108,6 +111,21 @@ required:
> > - clocks
> > - interrupts
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,usbhs-r9a07g044
> > + then:
> > + properties:
> > + interrupts:
> > + items:
> > + - description: U2P_IXL_INT
> > + - description: U2P_INT_DMA[0]
> > + - description: U2P_INT_DMA[1]
> > + - description: U2P_INT_DMAERR
>
> else:
> properties:
> interrupts:
> maxItems: 1
OK. Will fix this in next version.
Cheers,
Biju
>
> > +
> > additionalProperties: false
> >
> > examples:
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2021-07-27 14:59 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20210719121938.6532-1-biju.das.jz@bp.renesas.com>
2021-07-19 12:19 ` [PATCH v4 01/10] dt-bindings: usb: generic-ohci: Document dr_mode property Biju Das
2021-07-19 12:19 ` [PATCH v4 02/10] dt-bindings: usb: generic-ehci: " Biju Das
2021-07-19 12:19 ` [PATCH v4 03/10] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings Biju Das
2021-07-19 15:27 ` Rob Herring
2021-07-20 11:26 ` Biju Das
2021-07-20 16:36 ` Rob Herring
2021-07-20 16:56 ` Biju Das
2021-07-26 22:26 ` Rob Herring
2021-07-19 12:19 ` [PATCH v4 04/10] reset: renesas: Add RZ/G2L usbphy control driver Biju Das
2021-07-27 7:55 ` Biju Das
2021-07-27 13:37 ` Philipp Zabel
2021-07-27 13:53 ` Biju Das
2021-07-27 13:58 ` Philipp Zabel
2021-07-19 12:19 ` [PATCH v4 05/10] arm64: configs: defconfig: Enable RZ/G2L USBPHY " Biju Das
2021-07-19 12:19 ` [PATCH v4 06/10] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-07-26 22:28 ` Rob Herring
2021-07-27 14:58 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 07/10] phy: renesas: phy-rcar-gen3-usb2: Add OTG support for RZ/G2L Biju Das
2021-07-19 12:19 ` [PATCH v4 08/10] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
2021-07-19 12:19 ` [PATCH v4 09/10] dt-bindings: usb: renesas,usbhs: Document RZ/G2L bindings Biju Das
2021-07-26 22:30 ` Rob Herring
2021-07-27 14:59 ` Biju Das
2021-07-19 12:19 ` [PATCH v4 10/10] arm64: dts: renesas: r9a07g044: Add USB2.0 device support Biju Das
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