From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base
Date: Fri, 9 Nov 2018 00:42:56 -0800 [thread overview]
Message-ID: <20181109084256.GA6508@infradead.org> (raw)
In-Reply-To: <20181022114517.22748-2-anup@brainfault.org>
On Mon, Oct 22, 2018 at 05:15:14PM +0530, Anup Patel wrote:
> This patch does following optimizations:
> 1. Pre-compute hart base for each context handler
> 2. Pre-compute enable base for each context handler
Why?
> 3. Have enable lock for each context handler instead
> of global plic_toggle_lock
Why? Also even if you want this it should be a separate patch.
> #define PRIORITY_BASE 0
> -#define PRIORITY_PER_ID 4
> +#define PRIORITY_PER_ID 4
Also please drop the random whitespace changes.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Thomas Gleixner <tglx@linutronix.de>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base
Date: Fri, 9 Nov 2018 00:42:56 -0800 [thread overview]
Message-ID: <20181109084256.GA6508@infradead.org> (raw)
Message-ID: <20181109084256.NqIB8k5qsi8k1k0ubOBZZE7jf4C3NeASSjlJMiUtzZU@z> (raw)
In-Reply-To: <20181022114517.22748-2-anup@brainfault.org>
On Mon, Oct 22, 2018 at 05:15:14PM +0530, Anup Patel wrote:
> This patch does following optimizations:
> 1. Pre-compute hart base for each context handler
> 2. Pre-compute enable base for each context handler
Why?
> 3. Have enable lock for each context handler instead
> of global plic_toggle_lock
Why? Also even if you want this it should be a separate patch.
> #define PRIORITY_BASE 0
> -#define PRIORITY_PER_ID 4
> +#define PRIORITY_PER_ID 4
Also please drop the random whitespace changes.
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next prev parent reply other threads:[~2018-11-09 8:42 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-22 11:45 [PATCH 0/4] IRQ affinity support in PLIC driver Anup Patel
2018-10-22 11:45 ` Anup Patel
2018-10-22 11:45 ` [PATCH 1/4] irqchip: sifive-plic: Pre-compute context hart base and enable base Anup Patel
2018-10-22 11:45 ` Anup Patel
2018-11-09 8:42 ` Christoph Hellwig [this message]
2018-11-09 8:42 ` Christoph Hellwig
2018-11-12 4:27 ` Anup Patel
2018-11-12 4:27 ` Anup Patel
2018-10-22 11:45 ` [PATCH 2/4] irqchip: sifive-plic: More flexible plic_irq_toggle() Anup Patel
2018-10-22 11:45 ` Anup Patel
2018-11-09 8:43 ` Christoph Hellwig
2018-11-09 8:43 ` Christoph Hellwig
2018-11-12 12:33 ` Anup Patel
2018-11-12 12:33 ` Anup Patel
2018-10-22 11:45 ` [PATCH 3/4] irqchip: sifive-plic: Differentiate between PLIC handler and context Anup Patel
2018-10-22 11:45 ` Anup Patel
2018-10-22 11:45 ` [PATCH 4/4] irqchip: sifive-plic: Implement irq_set_affinity() for SMP host Anup Patel
2018-10-22 11:45 ` Anup Patel
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