From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <Anup.Patel@wdc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <Atish.Patra@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h
Date: Tue, 23 Apr 2019 23:29:47 -0700 [thread overview]
Message-ID: <20190424062947.GB10400@infradead.org> (raw)
In-Reply-To: <20190415093648.7525-3-anup.patel@wdc.com>
On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote:
> This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
> defines to asm/csr.h. We also use these defines in kernel/irq.c and
> express SIE/SIP flags in-terms of SCAUSE interrupt causes.
I'm not a fan of this. For one this pollutes csr.h with bits not really
needed by most users, and it makes adding the M-mode nommu port which has
to use the M-mode causes much harder:
http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba
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next prev parent reply other threads:[~2019-04-24 6:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-15 9:37 [PATCH v3 0/3] Allow accessing CSR using CSR number Anup Patel
2019-04-15 9:37 ` [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel
2019-04-24 6:27 ` Christoph Hellwig
2019-04-15 9:37 ` [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel
2019-04-24 6:29 ` Christoph Hellwig [this message]
2019-04-24 6:45 ` Anup Patel
2019-04-24 15:01 ` Christoph Hellwig
2019-04-25 5:04 ` Anup Patel
2019-04-15 9:37 ` [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel
2019-04-24 6:30 ` Christoph Hellwig
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