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From: Atish Patra <atish.patra@wdc.com>
To: linux-kernel@vger.kernel.org
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Mike Rapoport <rppt@linux.ibm.com>,
	Atish Patra <atish.patra@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	linux-riscv@lists.infradead.org,
	Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v6 0/5] Add support for SBI v0.2
Date: Wed, 18 Dec 2019 13:39:13 -0800	[thread overview]
Message-ID: <20191218213918.16676-1-atish.patra@wdc.com> (raw)

The Supervisor Binary Interface(SBI) specification[1] now defines a
base extension that provides extendability to add future extensions
while maintaining backward compatibility with previous versions.
The new version is defined as 0.2 and older version is marked as 0.1.


This series adds support v0.2 and a unified calling convention
implementation between 0.1 and 0.2. It also add other SBI v0.2
functionality defined in [2]. The base support for SBI v0.2 is already
available in OpenSBI v0.5. This series needs additional patches[3] in
OpenSBI. 

Tested on both BBL, OpenSBI with/without the above patch series. 

[1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] https://github.com/riscv/riscv-sbi-doc/pull/27
[3] http://lists.infradead.org/pipermail/opensbi/2019-November/000738.html

Changes from v5->v6
1. Fixed few compilation issues around config.
2. Fixed hart mask generation issues for RFENCE & IPI extensions.

Changes from v4->v5
1. Fixed few minor comments related to static & inline.
2. Make sure that every patch is boot tested individually.

Changes from v3->v4.
1. Rebased on for-next.
2. Fixed issuses with checkpatch --strict.
3. Unfied all IPI/fence related functions.
4. Added Hfence related SBI calls.

Changes from v2->v3.
1. Moved v0.1 extensions to a new config.
2. Added support for relacement extensions of v0.1 extensions.

Changes from v1->v2
1. Removed the legacy calling convention.
2. Moved all SBI related calls to sbi.c.
3. Moved all SBI related macros to uapi.

Atish Patra (5):
RISC-V: Mark existing SBI as 0.1 SBI.
RISC-V: Add basic support for SBI v0.2
RISC-V: Add SBI v0.2 extension definitions
RISC-V: Introduce a new config for SBI v0.1
RISC-V: Implement new SBI v0.2 extensions

arch/riscv/Kconfig           |   6 +
arch/riscv/include/asm/sbi.h | 178 +++++++-----
arch/riscv/kernel/sbi.c      | 522 ++++++++++++++++++++++++++++++++++-
arch/riscv/kernel/setup.c    |   2 +
4 files changed, 635 insertions(+), 73 deletions(-)

--
2.24.0



             reply	other threads:[~2019-12-18 21:39 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-18 21:39 Atish Patra [this message]
2019-12-18 21:39 ` [PATCH v6 1/5] RISC-V: Mark existing SBI as 0.1 SBI Atish Patra
2019-12-18 21:39 ` [PATCH v6 2/5] RISC-V: Add basic support for SBI v0.2 Atish Patra
2019-12-18 21:39 ` [PATCH v6 3/5] RISC-V: Add SBI v0.2 extension definitions Atish Patra
2019-12-19  6:55   ` Anup Patel
2019-12-18 21:39 ` [PATCH v6 4/5] RISC-V: Introduce a new config for SBI v0.1 Atish Patra
2019-12-18 21:39 ` [PATCH v6 5/5] RISC-V: Implement new SBI v0.2 extensions Atish Patra
2020-01-15 20:34 ` [PATCH v6 3/5] RISC-V: Add SBI v0.2 extension definitions Palmer Dabbelt
2020-01-15 20:36 ` [PATCH v6 0/5] Add support for SBI v0.2 Palmer Dabbelt
2020-01-16  0:43   ` Anup Patel

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