From: Heiko Stuebner <heiko@sntech.de>
To: palmer@dabbelt.com, paul.walmsley@sifive.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, hch@lst.de, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
rdunlap@infradead.org, Heiko Stuebner <heiko@sntech.de>,
Rob Herring <robh@kernel.org>
Subject: [PATCH 2/4] dt-bindings: riscv: document cbom-block-size
Date: Sun, 19 Jun 2022 22:32:10 +0200 [thread overview]
Message-ID: <20220619203212.3604485-3-heiko@sntech.de> (raw)
In-Reply-To: <20220619203212.3604485-1-heiko@sntech.de>
The Zicbom operates on a block-size defined for the cpu-core,
which does not necessarily match other cache-sizes used.
So add the necessary property for the system to know the core's
block-size.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..873dd12f6e89 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -63,6 +63,11 @@ properties:
- riscv,sv48
- riscv,none
+ riscv,cbom-block-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The blocksize in bytes for the Zicbom cache operations.
+
riscv,isa:
description:
Identifies the specific RISC-V instruction set architecture
--
2.35.1
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next prev parent reply other threads:[~2022-06-19 20:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-19 20:32 [PATCH v4 0/4] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-19 20:32 ` [PATCH 1/4] of: also handle dma-noncoherent in of_dma_is_coherent() Heiko Stuebner
2022-06-20 6:01 ` Christoph Hellwig
2022-06-20 16:33 ` Atish Patra
2022-06-20 18:11 ` Heiko Stuebner
2022-06-20 19:41 ` Atish Patra
2022-06-19 20:32 ` Heiko Stuebner [this message]
2022-06-19 20:32 ` [PATCH 3/4] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-20 6:16 ` Christoph Hellwig
2022-06-24 7:49 ` Heiko Stuebner
2022-06-19 20:32 ` [PATCH 4/4] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-29 1:29 ` Samuel Holland
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