From: Christoph Hellwig <hch@lst.de>
To: Heiko Stuebner <heiko@sntech.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
wefu@redhat.com, guoren@kernel.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, hch@lst.de, samuel@sholland.org,
atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr,
robh+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, drew@beagleboard.org,
rdunlap@infradead.org, Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 3/4] riscv: Implement Zicbom-based cache management operations
Date: Mon, 20 Jun 2022 08:16:07 +0200 [thread overview]
Message-ID: <20220620061607.GB10485@lst.de> (raw)
In-Reply-To: <20220619203212.3604485-4-heiko@sntech.de>
On Sun, Jun 19, 2022 at 10:32:11PM +0200, Heiko Stuebner wrote:
> +#ifdef CONFIG_RISCV_DMA_NONCOHERENT
> +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
> +#endif
This needs to be greater or equal to riscv_cbom_block_size, but the
core code requires a compile time constant here. So we'll need a big
fat comment here, and panic if riscv_cbom_block_size is >
L1_CACHE_BYTES/ARCH_DMA_MINALIGN in the code that queries
riscv_cbom_block_size.
Note that the arm64 folks are looking into making this variable or
killing it off in this current form, so things might be getting better
soon.
> +void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> + enum dma_data_direction dir)
> +{
> + void *vaddr = phys_to_virt(paddr);
> +
> + switch (dir) {
> + case DMA_TO_DEVICE:
> + ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);
> + break;
> + case DMA_FROM_DEVICE:
> + ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size);
> + break;
For this also see:
https://lore.kernel.org/all/20220606152150.GA31568@willie-the-truck/
and
https://lore.kernel.org/linux-arm-kernel/20220610151228.4562-1-will@kernel.org/T/
> +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> + const struct iommu_ops *iommu, bool coherent)
> +{
> + dev->dma_coherent = coherent;
> +}
This probably wants a sanity check warn if coherent if false without
any support for cache flushing as that will cause data corruption.
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next prev parent reply other threads:[~2022-06-20 6:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-19 20:32 [PATCH v4 0/4] riscv: implement Zicbom-based CMO instructions + the t-head variant Heiko Stuebner
2022-06-19 20:32 ` [PATCH 1/4] of: also handle dma-noncoherent in of_dma_is_coherent() Heiko Stuebner
2022-06-20 6:01 ` Christoph Hellwig
2022-06-20 16:33 ` Atish Patra
2022-06-20 18:11 ` Heiko Stuebner
2022-06-20 19:41 ` Atish Patra
2022-06-19 20:32 ` [PATCH 2/4] dt-bindings: riscv: document cbom-block-size Heiko Stuebner
2022-06-19 20:32 ` [PATCH 3/4] riscv: Implement Zicbom-based cache management operations Heiko Stuebner
2022-06-20 6:16 ` Christoph Hellwig [this message]
2022-06-24 7:49 ` Heiko Stuebner
2022-06-19 20:32 ` [PATCH 4/4] riscv: implement cache-management errata for T-Head SoCs Heiko Stuebner
2022-06-29 1:29 ` Samuel Holland
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