* [PATCH v4 1/7] dt-bindings: phy: Add StarFive JH7110 USB document
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-12 8:26 ` Krzysztof Kozlowski
2023-04-06 1:52 ` [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document Minda Chen
` (6 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
new file mode 100644
index 000000000000..80604dfe01f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 PHY
+
+maintainers:
+ - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-usb-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: usb 125m clock
+ - description: app 125m clock
+
+ clock-names:
+ items:
+ - const: 125m
+ - const: app_125
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x10200000 0x10000>;
+ clocks = <&syscrg 95>,
+ <&stgcrg 6>;
+ clock-names = "125m", "app_125";
+ #phy-cells = <0>;
+ };
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 1/7] dt-bindings: phy: Add StarFive JH7110 USB document
2023-04-06 1:52 ` [PATCH v4 1/7] dt-bindings: phy: Add StarFive JH7110 USB document Minda Chen
@ 2023-04-12 8:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-12 8:26 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 06/04/2023 03:52, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 2.0 PHY dt-binding.
Not much improvements in the subject. I asked to drop, not replace
document with document.
"Add StarFive JH7110 USB PHY"
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> new file mode 100644
> index 000000000000..80604dfe01f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive USB 2.0 PHY
Missing model name.
> +
> +maintainers:
> + - Minda Chen <minda.chen@starfivetech.com>
> +
Best regards,
Krzysztof
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
2023-04-06 1:52 ` [PATCH v4 1/7] dt-bindings: phy: Add StarFive JH7110 USB document Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-12 8:28 ` Krzysztof Kozlowski
2023-04-06 1:52 ` [PATCH v4 3/7] phy: starfive: add JH7110 USB 2.0 PHY driver Minda Chen
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
new file mode 100644
index 000000000000..1b868f75ddae
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive PCIe 2.0 PHY
+
+maintainers:
+ - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ starfive,sys-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller sys_syscon node.
+ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
+ description:
+ The phandle to System Register Controller syscon node and the PHY connect offset
+ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
+ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x10210000 0x10000>;
+ #phy-cells = <0>;
+ starfive,sys-syscon = <&sys_syscon 0x18>;
+ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
+ };
--
2.17.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document
2023-04-06 1:52 ` [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document Minda Chen
@ 2023-04-12 8:28 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-12 8:28 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 06/04/2023 03:52, Minda Chen wrote:
> Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
> PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
Subject: drop second/last, redundant "document". The "dt-bindings"
prefix is already stating that this is documentation.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++
> 1 file changed, 58 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> new file mode 100644
> index 000000000000..1b868f75ddae
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive PCIe 2.0 PHY
JH7110
Unless you plan to add here more compatibles, but then use enum for
compatible, not const.
> +
> +maintainers:
> + - Minda Chen <minda.chen@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-pcie-phy
> +
> + reg:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + starfive,sys-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle to System Register Controller sys_syscon node.
> + - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
No improvements here.
> + description:
> + The phandle to System Register Controller syscon node and the PHY connect offset
> + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
> +
> + starfive,stg-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: phandle to System Register Controller stg_syscon node.
> + - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
> + - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
No improvements.
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 3/7] phy: starfive: add JH7110 USB 2.0 PHY driver.
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
2023-04-06 1:52 ` [PATCH v4 1/7] dt-bindings: phy: Add StarFive JH7110 USB document Minda Chen
2023-04-06 1:52 ` [PATCH v4 2/7] dt-bindings: phy: Add StarFive JH7110 PCIe document Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-06 1:52 ` [PATCH v4 4/7] phy: starfive: add JH7110 PCIE " Minda Chen
` (4 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Add Starfive JH7110 SoC USB 2.0 PHY driver support.
USB 2.0 PHY default connect to Cadence USB controller.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
MAINTAINERS | 7 ++
drivers/phy/starfive/Kconfig | 11 ++
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++++++++++++++++++++
4 files changed, 180 insertions(+)
create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1aef5ba46d71..9da352084403 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19968,6 +19968,13 @@ M: William Qiu <william.qiu@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+STARFIVE JH71X0 USB PHY DRIVER
+M: Emil Renner Berthing <kernel@esmil.dk>
+M: Minda Chen <minda.chen@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F: drivers/phy/starfive/phy-jh7110-usb.c
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f989b8ff8bcb..2c013c390dee 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -11,3 +11,14 @@ config PHY_STARFIVE_DPHY_RX
Choose this option if you have a StarFive D-PHY in your
system. If M is selected, the module will be called
phy-starfive-dphy-rx.
+
+config PHY_STARFIVE_JH7110_USB
+ tristate "Starfive JH7110 USB 2.0 PHY support"
+ depends on USB_SUPPORT
+ select GENERIC_PHY
+ select USB_PHY
+ help
+ Enable this to support the StarFive USB 2.0 PHY,
+ used with the Cadence USB controller.
+ If M is selected, the module will be called
+ phy-jh7110-usb.ko.
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 7ec576cb30ae..176443852f4d 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c
new file mode 100644
index 000000000000..fe2cec39e5d3
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2023 Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/usb/of.h>
+
+#define USB_125M_CLK_RATE 125000000
+#define USB_LS_KEEPALIVE_OFF 0x4
+#define USB_LS_KEEPALIVE_ENABLE BIT(4)
+
+struct jh7110_usb2_phy {
+ struct phy *phy;
+ void __iomem *regs;
+ struct clk *usb_125m_clk;
+ struct clk *app_125;
+ enum phy_mode mode;
+};
+
+static void jh7110_usb2_mode_set(struct jh7110_usb2_phy *phy)
+{
+ unsigned int val;
+
+ if (phy->mode != PHY_MODE_USB_HOST) {
+ /* Enable the LS speed keep-alive signal */
+ val = readl(phy->regs + USB_LS_KEEPALIVE_OFF);
+ val |= USB_LS_KEEPALIVE_ENABLE;
+ writel(val, phy->regs + USB_LS_KEEPALIVE_OFF);
+ }
+}
+
+static int jh7110_usb2_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (mode != phy->mode) {
+ dev_info(&_phy->dev, "Changing phy to %d\n", mode);
+ phy->mode = mode;
+ jh7110_usb2_mode_set(phy);
+ }
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+ int ret;
+
+ ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(phy->app_125);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy);
+
+ clk_disable_unprepare(phy->app_125);
+
+ return 0;
+}
+
+static const struct phy_ops jh7110_usb2_phy_ops = {
+ .init = jh7110_usb2_phy_init,
+ .exit = jh7110_usb2_phy_exit,
+ .set_mode = jh7110_usb2_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int jh7110_usb_phy_probe(struct platform_device *pdev)
+{
+ struct jh7110_usb2_phy *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->usb_125m_clk = devm_clk_get(dev, "125m");
+ if (IS_ERR(phy->usb_125m_clk))
+ return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk),
+ "Failed to get 125m clock\n");
+
+ phy->app_125 = devm_clk_get(dev, "app_125");
+ if (IS_ERR(phy->app_125))
+ return dev_err_probe(dev, PTR_ERR(phy->app_125),
+ "Failed to get app 125m clock\n");
+
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->regs))
+ return dev_err_probe(dev, PTR_ERR(phy->regs),
+ "Failed to map phy base\n");
+
+ phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops);
+ if (IS_ERR(phy->phy))
+ return dev_err_probe(dev, PTR_ERR(phy->phy),
+ "Failed to create phy\n");
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy->phy, phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int jh7110_usb_phy_remove(struct platform_device *pdev)
+{
+ struct jh7110_usb2_phy *phy = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(phy->app_125);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_usb_phy_of_match[] = {
+ { .compatible = "starfive,jh7110-usb-phy" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match);
+
+static struct platform_driver jh7110_usb_phy_driver = {
+ .probe = jh7110_usb_phy_probe,
+ .remove = jh7110_usb_phy_remove,
+ .driver = {
+ .of_match_table = jh7110_usb_phy_of_match,
+ .name = "jh7110-usb-phy",
+ }
+};
+module_platform_driver(jh7110_usb_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 4/7] phy: starfive: add JH7110 PCIE 2.0 PHY driver.
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
` (2 preceding siblings ...)
2023-04-06 1:52 ` [PATCH v4 3/7] phy: starfive: add JH7110 USB 2.0 PHY driver Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-06 1:52 ` [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas Minda Chen
` (3 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Add Starfive JH7110 SoC PCIe 2.0 driver support.
PCIe 2.0 PHY default connect to PCIe controller.
But pcie0 PHY can connect to USB 3.0 controlller.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
MAINTAINERS | 4 +-
drivers/phy/starfive/Kconfig | 11 ++
drivers/phy/starfive/Makefile | 1 +
drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++++++++++++++++++
4 files changed, 212 insertions(+), 1 deletion(-)
create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 9da352084403..d98b70d62fd4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19968,11 +19968,13 @@ M: William Qiu <william.qiu@starfivetech.com>
S: Supported
F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
-STARFIVE JH71X0 USB PHY DRIVER
+STARFIVE JH71X0 PCIE AND USB PHY DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>
M: Minda Chen <minda.chen@starfivetech.com>
S: Supported
+F: Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
+F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
STATIC BRANCH/CALL
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index 2c013c390dee..c21c21d284a6 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -12,6 +12,17 @@ config PHY_STARFIVE_DPHY_RX
system. If M is selected, the module will be called
phy-starfive-dphy-rx.
+config PHY_STARFIVE_JH7110_PCIE
+ tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
+ depends on USB_SUPPORT
+ select GENERIC_PHY
+ select USB_PHY
+ help
+ Enable this to support the StarFive PCIe 2.0 PHY,
+ or used as USB 3.0 PHY.
+ If M is selected, the module will be called
+ phy-jh7110-pcie.ko.
+
config PHY_STARFIVE_JH7110_USB
tristate "Starfive JH7110 USB 2.0 PHY support"
depends on USB_SUPPORT
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index 176443852f4d..03a55aad53a2 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 000000000000..725815aabe74
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2023 Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#define PCIE_KVCO_LEVEL_OFF (0x28)
+#define PCIE_USB3_PHY_PLL_CTL_OFF (0x7c)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF (0x80)
+#define PCIE_USB3_PHY_ENABLE BIT(4)
+#define PHY_KVCO_FINE_TUNE_LEVEL 0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define USB_PDRSTN_SPLIT BIT(17)
+
+#define PCIE_CKREF_SRC_MASK GENMASK(19, 18)
+#define PCIE_CLK_SEL_MASK GENMASK(21, 20)
+#define PCIE_PHY_MODE BIT(20)
+#define PCIE_PHY_MODE_MASK GENMASK(21, 20)
+#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2)
+#define PCIE_USB3_RATE_MASK GENMASK(6, 5)
+#define PCIE_USB3_RX_STANDBY_MASK BIT(7)
+#define PCIE_USB3_PHY_ENABLE BIT(4)
+
+struct jh7110_pcie_phy {
+ struct phy *phy;
+ struct regmap *stg_syscon;
+ struct regmap *sys_syscon;
+ void __iomem *regs;
+ u32 sys_phy_connect;
+ u32 stg_pcie_mode;
+ u32 stg_pcie_usb;
+ enum phy_mode mode;
+};
+
+static int jh7110_usb3_mode_set(struct jh7110_pcie_phy *data)
+{
+ if (!data->stg_syscon || !data->sys_syscon) {
+ dev_info(&data->phy->dev, "don't support usb3 mode\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+ PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_BUS_WIDTH_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_RATE_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_RX_STANDBY_MASK, 0);
+ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+ PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
+
+ /* Connect usb 3.0 phy mode */
+ regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+ USB_PDRSTN_SPLIT, 0);
+
+ /* Configuare spread-spectrum mode: down-spread-spectrum */
+ writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
+
+ return 0;
+}
+
+static void jh7110_pcie_mode_set(struct jh7110_pcie_phy *phy)
+{
+ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+ enum phy_mode mode, int submode)
+{
+ struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
+ int ret;
+
+ if (mode != phy->mode) {
+ switch (mode) {
+ case PHY_MODE_USB_HOST:
+ case PHY_MODE_USB_DEVICE:
+ case PHY_MODE_USB_OTG:
+ ret = jh7110_usb3_mode_set(phy);
+ if (ret)
+ return ret;
+ break;
+ case PHY_MODE_PCIE:
+ jh7110_pcie_mode_set(phy);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ dev_info(&_phy->dev, "Changing phy mode to %d\n", mode);
+ phy->mode = mode;
+ }
+
+ return 0;
+}
+
+static int jh7110_pcie_phy_init(struct phy *_phy)
+{
+ return 0;
+}
+
+static int jh7110_pcie_phy_exit(struct phy *_phy)
+{
+ return 0;
+}
+
+static const struct phy_ops jh7110_pcie_phy_ops = {
+ .init = jh7110_pcie_phy_init,
+ .exit = jh7110_pcie_phy_exit,
+ .set_mode = jh7110_pcie_phy_set_mode,
+ .owner = THIS_MODULE,
+};
+
+static int jh7110_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct jh7110_pcie_phy *phy;
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ u32 args[3];
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->regs))
+ return PTR_ERR(phy->regs);
+
+ phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops);
+ if (IS_ERR(phy->phy))
+ return dev_err_probe(dev, PTR_ERR(phy->regs),
+ "Failed to map phy base\n");
+
+ phy->sys_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,sys-syscon", 1, args);
+
+ if (!IS_ERR_OR_NULL(phy->sys_syscon))
+ phy->sys_phy_connect = args[0];
+ else
+ phy->sys_syscon = NULL;
+
+ phy->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,stg-syscon", 2, args);
+
+ if (!IS_ERR_OR_NULL(phy->stg_syscon)) {
+ phy->stg_pcie_mode = args[0];
+ phy->stg_pcie_usb = args[1];
+ } else
+ phy->stg_syscon = NULL;
+
+ platform_set_drvdata(pdev, phy);
+ phy_set_drvdata(phy->phy, phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static int jh7110_pcie_phy_remove(struct platform_device *pdev)
+{
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_pcie_phy_of_match[] = {
+ { .compatible = "starfive,jh7110-pcie-phy" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match);
+
+static struct platform_driver jh7110_pcie_phy_driver = {
+ .probe = jh7110_pcie_phy_probe,
+ .remove = jh7110_pcie_phy_remove,
+ .driver = {
+ .of_match_table = jh7110_pcie_phy_of_match,
+ .name = "jh7110-pcie-phy",
+ }
+};
+module_platform_driver(jh7110_pcie_phy_driver);
+
+MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver");
+MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
` (3 preceding siblings ...)
2023-04-06 1:52 ` [PATCH v4 4/7] phy: starfive: add JH7110 PCIE " Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-12 8:32 ` Krzysztof Kozlowski
2023-04-06 1:52 ` [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver Minda Chen
` (2 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
StarFive JH7110 platforms USB have a wrapper module around
the Cadence USBSS-DRD controller. Add binding information doc
for that.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Peter Chen <peter.chen@kernel.org>
---
.../bindings/usb/starfive,jh7110-usb.yaml | 136 ++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
new file mode 100644
index 000000000000..c8b30b583854
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
+
+maintainers:
+ - Minda Chen <minda.chen@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-usb
+
+ reg:
+ items:
+ - description: OTG controller registers
+ - description: XHCI Host controller registers
+ - description: DEVICE controller registers
+
+ reg-names:
+ items:
+ - const: otg
+ - const: xhci
+ - const: dev
+
+ interrupts:
+ items:
+ - description: XHCI host controller interrupt
+ - description: Device controller interrupt
+ - description: OTG/DRD controller interrupt
+
+ interrupt-names:
+ items:
+ - const: host
+ - const: peripheral
+ - const: otg
+
+ clocks:
+ items:
+ - description: lpm clock
+ - description: stb clock
+ - description: apb clock
+ - description: axi clock
+ - description: utmi apb clock
+
+ clock-names:
+ items:
+ - const: lpm
+ - const: stb
+ - const: apb
+ - const: axi
+ - const: utmi_apb
+
+ resets:
+ items:
+ - description: PWRUP reset
+ - description: APB clock reset
+ - description: AXI clock reset
+ - description: UTMI_APB clock reset
+
+ reset-names:
+ items:
+ - const: pwrup
+ - const: apb
+ - const: axi
+ - const: utmi
+
+ starfive,stg-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle to System Register Controller stg_syscon node.
+ - description: register offset of STG_SYSCONSAIF__SYSCFG register for USB.
+ description:
+ The phandle to System Register Controller syscon node and the offset
+ of STG_SYSCONSAIF__SYSCFG register for USB.
+
+ dr_mode:
+ enum: [host, otg, peripheral]
+
+ phys:
+ minItems: 1
+ maxItems: 2
+
+ phy-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ anyOf:
+ - const: usb2-phy
+ - const: usb3-phy
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - resets
+ - starfive,stg-syscon
+ - dr_mode
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ reg = <0x0 0x10100000 0x0 0x10000>,
+ <0x0 0x10110000 0x0 0x10000>,
+ <0x0 0x10120000 0x0 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ clocks = <&syscrg 4>,
+ <&stgcrg 5>,
+ <&stgcrg 1>,
+ <&stgcrg 3>,
+ <&stgcrg 2>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg 10>,
+ <&stgcrg 8>,
+ <&stgcrg 7>,
+ <&stgcrg 9>;
+ reset-names = "pwrup", "apb", "axi", "utmi";
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ dr_mode = "host";
+ };
+ };
--
2.17.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
2023-04-06 1:52 ` [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas Minda Chen
@ 2023-04-12 8:32 ` Krzysztof Kozlowski
2023-04-13 10:42 ` Minda Chen
0 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-12 8:32 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 06/04/2023 03:52, Minda Chen wrote:
> StarFive JH7110 platforms USB have a wrapper module around
> the Cadence USBSS-DRD controller. Add binding information doc
> for that.
That's one of the most redundant subjects I saw. You basically used four
words for one meaning. These are not exactly synonyms, but they all are
either imprecise or meaning the same.
Subject: drop second/last, redundant "Bindings YAML schemas". The
"dt-bindings" prefix is already stating that these are bindings.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> Reviewed-by: Peter Chen <peter.chen@kernel.org>
> ---
> .../bindings/usb/starfive,jh7110-usb.yaml | 136 ++++++++++++++++++
> 1 file changed, 136 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> new file mode 100644
> index 000000000000..c8b30b583854
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
What do you wrap here? Are you sure this is a wrapper? I think this is
just USB controller?
> +
> +maintainers:
> + - Minda Chen <minda.chen@starfivetech.com>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-usb
> +
> + reg:
> + items:
> + - description: OTG controller registers
> + - description: XHCI Host controller registers
> + - description: DEVICE controller registers
> +
> + reg-names:
> + items:
> + - const: otg
> + - const: xhci
> + - const: dev
> +
> + interrupts:
> + items:
> + - description: XHCI host controller interrupt
> + - description: Device controller interrupt
> + - description: OTG/DRD controller interrupt
> +
> + interrupt-names:
> + items:
> + - const: host
> + - const: peripheral
> + - const: otg
> +
> + clocks:
> + items:
> + - description: lpm clock
> + - description: stb clock
> + - description: apb clock
> + - description: axi clock
> + - description: utmi apb clock
> +
> + clock-names:
> + items:
> + - const: lpm
> + - const: stb
> + - const: apb
> + - const: axi
> + - const: utmi_apb
> +
> + resets:
> + items:
> + - description: PWRUP reset
> + - description: APB clock reset
> + - description: AXI clock reset
> + - description: UTMI_APB clock reset
> +
> + reset-names:
> + items:
> + - const: pwrup
> + - const: apb
> + - const: axi
> + - const: utmi
> +
> + starfive,stg-syscon:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
Same problem as for other patches.
> + - description: phandle to System Register Controller stg_syscon node.
> + - description: register offset of STG_SYSCONSAIF__SYSCFG register for USB.
> + description:
> + The phandle to System Register Controller syscon node and the offset
> + of STG_SYSCONSAIF__SYSCFG register for USB.
> +
Best regards,
Krzysztof
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
2023-04-12 8:32 ` Krzysztof Kozlowski
@ 2023-04-13 10:42 ` Minda Chen
0 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-13 10:42 UTC (permalink / raw)
To: Krzysztof Kozlowski, Emil Renner Berthing, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Pawel Laszczak, Greg Kroah-Hartman,
Peter Chen, Roger Quadros, Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 2023/4/12 16:32, Krzysztof Kozlowski wrote:
> On 06/04/2023 03:52, Minda Chen wrote:
>> StarFive JH7110 platforms USB have a wrapper module around
>> the Cadence USBSS-DRD controller. Add binding information doc
>> for that.
>
> That's one of the most redundant subjects I saw. You basically used four
> words for one meaning. These are not exactly synonyms, but they all are
> either imprecise or meaning the same.
>
> Subject: drop second/last, redundant "Bindings YAML schemas". The
> "dt-bindings" prefix is already stating that these are bindings.
>
>
ok
>
>>
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> Reviewed-by: Peter Chen <peter.chen@kernel.org>
>> ---
>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 ++++++++++++++++++
>> 1 file changed, 136 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> new file mode 100644
>> index 000000000000..c8b30b583854
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> @@ -0,0 +1,136 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
>
> What do you wrap here? Are you sure this is a wrapper? I think this is
> just USB controller?
>
Since the previous version is wrapper module. I forgot change this.
I will change to "StarFive JH7110 Cadence USBSS-DRD SoC controller"
>> +
>> +maintainers:
>> + - Minda Chen <minda.chen@starfivetech.com>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-usb
>> +
>> + reg:
>> + items:
>> + - description: OTG controller registers
>> + - description: XHCI Host controller registers
>> + - description: DEVICE controller registers
>> +
>> + reg-names:
>> + items:
>> + - const: otg
>> + - const: xhci
>> + - const: dev
>> +
>> + interrupts:
>> + items:
>> + - description: XHCI host controller interrupt
>> + - description: Device controller interrupt
>> + - description: OTG/DRD controller interrupt
>> +
>> + interrupt-names:
>> + items:
>> + - const: host
>> + - const: peripheral
>> + - const: otg
>> +
>> + clocks:
>> + items:
>> + - description: lpm clock
>> + - description: stb clock
>> + - description: apb clock
>> + - description: axi clock
>> + - description: utmi apb clock
>> +
>> + clock-names:
>> + items:
>> + - const: lpm
>> + - const: stb
>> + - const: apb
>> + - const: axi
>> + - const: utmi_apb
>> +
>> + resets:
>> + items:
>> + - description: PWRUP reset
>> + - description: APB clock reset
>> + - description: AXI clock reset
>> + - description: UTMI_APB clock reset
>> +
>> + reset-names:
>> + items:
>> + - const: pwrup
>> + - const: apb
>> + - const: axi
>> + - const: utmi
>> +
>> + starfive,stg-syscon:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + items:
>
> Same problem as for other patches.
>
I am sorry about this. I should change this in this version.
PCIe PHY dt-binding doc will be also changed.
>> + - description: phandle to System Register Controller stg_syscon node.
>> + - description: register offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> + description:
>> + The phandle to System Register Controller syscon node and the offset
>> + of STG_SYSCONSAIF__SYSCFG register for USB.
>> +
>
>
> Best regards,
> Krzysztof
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver.
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
` (4 preceding siblings ...)
2023-04-06 1:52 ` [PATCH v4 5/7] dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-11 1:01 ` Peter Chen
2023-04-06 1:52 ` [PATCH v4 7/7] riscv: dts: starfive: add USB dts configuration for JH7110 Minda Chen
2023-04-12 8:26 ` [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Krzysztof Kozlowski
7 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Adds Specific Glue layer to support USB peripherals on
StarFive JH7110 SoC.
There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/usb/cdns3/Kconfig | 11 +
drivers/usb/cdns3/Makefile | 1 +
drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
drivers/usb/cdns3/core.h | 3 +
5 files changed, 400 insertions(+)
create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d98b70d62fd4..0610bbf921bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
+STARFIVE JH71X0 USB DRIVERS
+M: Emil Renner Berthing <kernel@esmil.dk>
+M: Minda Chen <minda.chen@starfivetech.com>
+S: Maintained
+F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
+F: drivers/usb/cdns3/cdns3-starfive.c
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index b98ca0a1352a..0a514b591527 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -78,6 +78,17 @@ config USB_CDNS3_IMX
For example, imx8qm and imx8qxp.
+config USB_CDNS3_STARFIVE
+ tristate "Cadence USB3 support on StarFive SoC platforms"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ help
+ Say 'Y' or 'M' here if you are building for StarFive SoCs
+ platforms that contain Cadence USB3 controller core.
+
+ e.g. JH7110.
+
+ If you choose to build this driver as module it will
+ be dynamically linked and module will be called cdns3-starfive.ko
endif
if USB_CDNS_SUPPORT
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 61edb2f89276..48dfae75b5aa 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -24,6 +24,7 @@ endif
obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
+obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
cdnsp-udc-pci-y := cdnsp-pci.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 000000000000..925209a97bf9
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,378 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ * Author: Mason Huo <mason.huo@starfivetech.com>
+ * Author: Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/usb/otg.h>
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST BIT(19)
+#define USB_SUSPENDM_MASK BIT(19)
+#define CDNS_IRQ_WAKEUP_INDEX 3
+
+struct cdns_starfive {
+ struct device *dev;
+ struct phy *usb2_phy;
+ struct phy *usb3_phy;
+ struct regmap *stg_syscon;
+ struct reset_control *resets;
+ struct clk_bulk_data *clks;
+ int num_clks;
+ enum phy_mode phy_mode;
+ u32 stg_usb_mode;
+};
+
+static int set_phy_power_on(struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = phy_power_on(data->usb2_phy);
+ if (ret)
+ return ret;
+
+ ret = phy_power_on(data->usb3_phy);
+ if (ret)
+ phy_power_off(data->usb2_phy);
+
+ return ret;
+}
+
+static void set_phy_power_off(struct cdns_starfive *data)
+{
+ phy_power_off(data->usb3_phy);
+ phy_power_off(data->usb2_phy);
+}
+
+static void cdns_mode_init(struct platform_device *pdev,
+ struct cdns_starfive *data)
+{
+ enum usb_dr_mode mode;
+
+ mode = usb_get_dr_mode(&pdev->dev);
+
+ switch (mode) {
+ case USB_DR_MODE_HOST:
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_STRAP_MASK,
+ USB_STRAP_HOST);
+ regmap_update_bits(data->stg_syscon,
+ data->stg_usb_mode,
+ USB_SUSPENDM_MASK,
+ USB_SUSPENDM_HOST);
+ data->phy_mode = PHY_MODE_USB_HOST;
+ break;
+
+ case USB_DR_MODE_PERIPHERAL:
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_STRAP_MASK, USB_STRAP_DEVICE);
+ regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+ USB_SUSPENDM_MASK, 0);
+ data->phy_mode = PHY_MODE_USB_DEVICE;
+ break;
+
+ case USB_DR_MODE_OTG:
+ data->phy_mode = PHY_MODE_USB_OTG;
+ default:
+ break;
+ }
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+ int ret;
+
+ data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
+ if (data->num_clks < 0)
+ return dev_err_probe(data->dev, -ENODEV,
+ "Failed to get clocks\n");
+
+ data->resets = devm_reset_control_array_get_exclusive(data->dev);
+ if (IS_ERR(data->resets)) {
+ return dev_err_probe(data->dev, PTR_ERR(data->resets),
+ "Failed to get resets");
+ }
+
+ ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+ if (ret)
+ return dev_err_probe(data->dev, ret,
+ "failed to enable clocks\n");
+
+ ret = reset_control_deassert(data->resets);
+ if (ret) {
+ ret = dev_err_probe(data->dev, ret,
+ "failed to reset clocks\n");
+ goto err_clk_init;
+ }
+
+ return ret;
+
+err_clk_init:
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ return ret;
+}
+
+static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
+{
+ int ret;
+
+ ret = phy_init(data->usb2_phy);
+ if (ret)
+ return ret;
+
+ ret = phy_init(data->usb3_phy);
+ if (ret)
+ goto err_phy3_init;
+
+ ret = set_phy_power_on(data);
+ if (ret)
+ goto err_phy_power_on;
+
+ phy_set_mode(data->usb2_phy, data->phy_mode);
+ phy_set_mode(data->usb3_phy, data->phy_mode);
+
+ return 0;
+
+err_phy_power_on:
+ phy_exit(data->usb3_phy);
+err_phy3_init:
+ phy_exit(data->usb2_phy);
+ return ret;
+}
+
+static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
+ struct cdns_starfive *data)
+{
+ struct platform_device *cdns3;
+ struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
+ struct device *dev = &pdev->dev;
+ const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
+ const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
+ int i, ret, res_idx = 0;
+
+ cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
+ if (!cdns3)
+ return dev_err_probe(dev, -ENOMEM,
+ "couldn't alloc cdns3 usb device\n");
+
+ cdns3->dev.parent = dev;
+ memset(cdns_res, 0, sizeof(cdns_res));
+
+ for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
+ if (!res) {
+ ret = dev_err_probe(dev,
+ -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
+ goto free_memory;
+ }
+ cdns_res[res_idx] = *res;
+ res_idx++;
+ }
+
+ for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
+ if (i == CDNS_IRQ_WAKEUP_INDEX) {
+ ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
+ if (ret < 0)
+ continue;
+ } else {
+ ret = platform_get_irq_byname(pdev, irq_name[i]);
+ if (ret < 0) {
+ dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
+ goto free_memory;
+ }
+ }
+ cdns_res[res_idx].start = ret;
+ cdns_res[res_idx].end = ret;
+ cdns_res[res_idx].flags = IORESOURCE_IRQ;
+ cdns_res[res_idx].name = irq_name[i];
+ res_idx++;
+ }
+
+ ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
+ if (ret) {
+ dev_err(dev, "couldn't add res to cdns3 device\n");
+ goto free_memory;
+ }
+
+ ret = platform_device_add(cdns3);
+ if (ret) {
+ dev_err(dev, "failed to register cdns3 device\n");
+ goto free_memory;
+ }
+
+ return ret;
+free_memory:
+ platform_device_put(cdns3);
+ return ret;
+}
+
+static int cdns_starfive_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cdns_starfive *data;
+ unsigned int args;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, data);
+
+ data->dev = dev;
+
+ data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+ "starfive,stg-syscon", 1, &args);
+
+ if (IS_ERR(data->stg_syscon))
+ return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
+ "Failed to parse starfive,stg-syscon\n");
+
+ data->stg_usb_mode = args;
+
+ cdns_mode_init(pdev, data);
+
+ ret = cdns_clk_rst_init(data);
+ if (ret)
+ return ret;
+
+ data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
+ if (IS_ERR(data->usb2_phy))
+ return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
+ "Failed to parse usb2 phy\n");
+
+ data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
+ if (IS_ERR(data->usb3_phy))
+ return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
+ "Failed to parse usb3 phy\n");
+
+ cdns3_starfive_phy_init(dev, data);
+
+ ret = cdns3_starfive_platform_device_add(pdev, data);
+ if (ret) {
+ set_phy_power_off(data);
+ phy_exit(data->usb3_phy);
+ phy_exit(data->usb2_phy);
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ return dev_err_probe(dev, ret, "Failed to create children\n");
+ }
+
+ device_set_wakeup_capable(dev, true);
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
+
+ return 0;
+}
+
+static int cdns_starfive_remove_core(struct device *dev, void *c)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+
+ platform_device_unregister(pdev);
+
+ return 0;
+}
+
+static int cdns_starfive_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+
+ pm_runtime_get_sync(dev);
+ device_for_each_child(dev, NULL, cdns_starfive_remove_core);
+
+ set_phy_power_off(data);
+ phy_exit(data->usb2_phy);
+ phy_exit(data->usb3_phy);
+
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+ pm_runtime_disable(dev);
+ pm_runtime_put_noidle(dev);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int cdns_starfive_resume(struct device *dev)
+{
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+ if (ret)
+ return ret;
+
+ ret = reset_control_deassert(data->resets);
+ if (ret)
+ return ret;
+
+ ret = cdns3_starfive_phy_init(dev, data);
+
+ return ret;
+}
+
+static int cdns_starfive_suspend(struct device *dev)
+{
+ struct cdns_starfive *data = dev_get_drvdata(dev);
+
+ set_phy_power_off(data);
+ phy_exit(data->usb2_phy);
+ phy_exit(data->usb3_phy);
+ reset_control_assert(data->resets);
+ clk_bulk_disable_unprepare(data->num_clks, data->clks);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops cdns_starfive_pm_ops = {
+ SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
+};
+
+static const struct of_device_id cdns_starfive_of_match[] = {
+ { .compatible = "starfive,jh7110-usb", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
+
+static struct platform_driver cdns_starfive_driver = {
+ .probe = cdns_starfive_probe,
+ .remove = cdns_starfive_remove,
+ .driver = {
+ .name = "cdns3-starfive",
+ .of_match_table = cdns_starfive_of_match,
+ .pm = &cdns_starfive_pm_ops,
+ },
+};
+module_platform_driver(cdns_starfive_driver);
+
+MODULE_ALIAS("platform:cdns3-starfive");
+MODULE_AUTHOR("YanHong Wang <yanhong.wang@starfivetech.com>");
+MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
index 2d332a788871..8d44ab504898 100644
--- a/drivers/usb/cdns3/core.h
+++ b/drivers/usb/cdns3/core.h
@@ -38,6 +38,9 @@ struct cdns_role_driver {
};
#define CDNS_XHCI_RESOURCES_NUM 2
+#define CDNS_IOMEM_RESOURCES_NUM 3
+#define CDNS_IRQ_RESOURCES_NUM 4
+#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
struct cdns3_platform_data {
int (*platform_suspend)(struct device *dev,
--
2.17.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver.
2023-04-06 1:52 ` [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver Minda Chen
@ 2023-04-11 1:01 ` Peter Chen
2023-04-12 6:14 ` Minda Chen
0 siblings, 1 reply; 20+ messages in thread
From: Peter Chen @ 2023-04-11 1:01 UTC (permalink / raw)
To: Minda Chen
Cc: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Roger Quadros, Philipp Zabel,
devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 23-04-06 09:52:15, Minda Chen wrote:
> Adds Specific Glue layer to support USB peripherals on
> StarFive JH7110 SoC.
> There is a Cadence USB3 core for JH7110 SoCs, the cdns
> core is the child of this USB wrapper module device.
>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
> MAINTAINERS | 7 +
> drivers/usb/cdns3/Kconfig | 11 +
> drivers/usb/cdns3/Makefile | 1 +
> drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
> drivers/usb/cdns3/core.h | 3 +
> 5 files changed, 400 insertions(+)
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d98b70d62fd4..0610bbf921bb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> F: drivers/phy/starfive/phy-jh7110-pcie.c
> F: drivers/phy/starfive/phy-jh7110-usb.c
>
> +STARFIVE JH71X0 USB DRIVERS
> +M: Emil Renner Berthing <kernel@esmil.dk>
> +M: Minda Chen <minda.chen@starfivetech.com>
> +S: Maintained
> +F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> +F: drivers/usb/cdns3/cdns3-starfive.c
> +
> STATIC BRANCH/CALL
> M: Peter Zijlstra <peterz@infradead.org>
> M: Josh Poimboeuf <jpoimboe@kernel.org>
> diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
> index b98ca0a1352a..0a514b591527 100644
> --- a/drivers/usb/cdns3/Kconfig
> +++ b/drivers/usb/cdns3/Kconfig
> @@ -78,6 +78,17 @@ config USB_CDNS3_IMX
>
> For example, imx8qm and imx8qxp.
>
> +config USB_CDNS3_STARFIVE
> + tristate "Cadence USB3 support on StarFive SoC platforms"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + help
> + Say 'Y' or 'M' here if you are building for StarFive SoCs
> + platforms that contain Cadence USB3 controller core.
> +
> + e.g. JH7110.
> +
> + If you choose to build this driver as module it will
> + be dynamically linked and module will be called cdns3-starfive.ko
> endif
>
> if USB_CDNS_SUPPORT
> diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
> index 61edb2f89276..48dfae75b5aa 100644
> --- a/drivers/usb/cdns3/Makefile
> +++ b/drivers/usb/cdns3/Makefile
> @@ -24,6 +24,7 @@ endif
> obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
> obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
> obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
> +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
>
> cdnsp-udc-pci-y := cdnsp-pci.o
>
> diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
> new file mode 100644
> index 000000000000..925209a97bf9
> --- /dev/null
> +++ b/drivers/usb/cdns3/cdns3-starfive.c
> @@ -0,0 +1,378 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/**
> + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
> + *
> + * Copyright (C) 2022 Starfive, Inc.
> + * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
> + * Author: Mason Huo <mason.huo@starfivetech.com>
> + * Author: Minda Chen <minda.chen@starfivetech.com>
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/kernel.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +#include <linux/of_platform.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/usb/otg.h>
> +#include "core.h"
> +
> +#define USB_STRAP_HOST BIT(17)
> +#define USB_STRAP_DEVICE BIT(18)
> +#define USB_STRAP_MASK GENMASK(18, 16)
> +
> +#define USB_SUSPENDM_HOST BIT(19)
> +#define USB_SUSPENDM_MASK BIT(19)
> +#define CDNS_IRQ_WAKEUP_INDEX 3
> +
> +struct cdns_starfive {
> + struct device *dev;
> + struct phy *usb2_phy;
> + struct phy *usb3_phy;
> + struct regmap *stg_syscon;
> + struct reset_control *resets;
> + struct clk_bulk_data *clks;
> + int num_clks;
> + enum phy_mode phy_mode;
> + u32 stg_usb_mode;
> +};
> +
> +static int set_phy_power_on(struct cdns_starfive *data)
> +{
> + int ret;
> +
> + ret = phy_power_on(data->usb2_phy);
> + if (ret)
> + return ret;
> +
> + ret = phy_power_on(data->usb3_phy);
> + if (ret)
> + phy_power_off(data->usb2_phy);
> +
> + return ret;
> +}
> +
> +static void set_phy_power_off(struct cdns_starfive *data)
> +{
> + phy_power_off(data->usb3_phy);
> + phy_power_off(data->usb2_phy);
> +}
> +
> +static void cdns_mode_init(struct platform_device *pdev,
> + struct cdns_starfive *data)
> +{
> + enum usb_dr_mode mode;
> +
> + mode = usb_get_dr_mode(&pdev->dev);
> +
> + switch (mode) {
> + case USB_DR_MODE_HOST:
> + regmap_update_bits(data->stg_syscon,
> + data->stg_usb_mode,
> + USB_STRAP_MASK,
> + USB_STRAP_HOST);
> + regmap_update_bits(data->stg_syscon,
> + data->stg_usb_mode,
> + USB_SUSPENDM_MASK,
> + USB_SUSPENDM_HOST);
> + data->phy_mode = PHY_MODE_USB_HOST;
> + break;
> +
> + case USB_DR_MODE_PERIPHERAL:
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_STRAP_MASK, USB_STRAP_DEVICE);
> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
> + USB_SUSPENDM_MASK, 0);
> + data->phy_mode = PHY_MODE_USB_DEVICE;
> + break;
> +
> + case USB_DR_MODE_OTG:
> + data->phy_mode = PHY_MODE_USB_OTG;
> + default:
> + break;
> + }
> +}
> +
> +static int cdns_clk_rst_init(struct cdns_starfive *data)
> +{
> + int ret;
> +
> + data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
> + if (data->num_clks < 0)
> + return dev_err_probe(data->dev, -ENODEV,
> + "Failed to get clocks\n");
> +
> + data->resets = devm_reset_control_array_get_exclusive(data->dev);
> + if (IS_ERR(data->resets)) {
> + return dev_err_probe(data->dev, PTR_ERR(data->resets),
> + "Failed to get resets");
> + }
> +
> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
> + if (ret)
> + return dev_err_probe(data->dev, ret,
> + "failed to enable clocks\n");
> +
> + ret = reset_control_deassert(data->resets);
> + if (ret) {
> + ret = dev_err_probe(data->dev, ret,
> + "failed to reset clocks\n");
> + goto err_clk_init;
> + }
> +
> + return ret;
> +
> +err_clk_init:
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + return ret;
> +}
> +
> +static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
> +{
> + int ret;
> +
> + ret = phy_init(data->usb2_phy);
> + if (ret)
> + return ret;
> +
> + ret = phy_init(data->usb3_phy);
> + if (ret)
> + goto err_phy3_init;
> +
> + ret = set_phy_power_on(data);
> + if (ret)
> + goto err_phy_power_on;
> +
> + phy_set_mode(data->usb2_phy, data->phy_mode);
> + phy_set_mode(data->usb3_phy, data->phy_mode);
> +
> + return 0;
> +
> +err_phy_power_on:
> + phy_exit(data->usb3_phy);
> +err_phy3_init:
> + phy_exit(data->usb2_phy);
> + return ret;
> +}
> +
> +static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
> + struct cdns_starfive *data)
> +{
> + struct platform_device *cdns3;
> + struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
> + struct device *dev = &pdev->dev;
> + const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
> + const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
> + int i, ret, res_idx = 0;
> +
> + cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
> + if (!cdns3)
> + return dev_err_probe(dev, -ENOMEM,
> + "couldn't alloc cdns3 usb device\n");
> +
> + cdns3->dev.parent = dev;
> + memset(cdns_res, 0, sizeof(cdns_res));
> +
> + for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
> + if (!res) {
> + ret = dev_err_probe(dev,
> + -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
> + goto free_memory;
> + }
> + cdns_res[res_idx] = *res;
> + res_idx++;
> + }
> +
> + for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
> + if (i == CDNS_IRQ_WAKEUP_INDEX) {
> + ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
> + if (ret < 0)
> + continue;
> + } else {
> + ret = platform_get_irq_byname(pdev, irq_name[i]);
> + if (ret < 0) {
> + dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
> + goto free_memory;
> + }
> + }
> + cdns_res[res_idx].start = ret;
> + cdns_res[res_idx].end = ret;
> + cdns_res[res_idx].flags = IORESOURCE_IRQ;
> + cdns_res[res_idx].name = irq_name[i];
> + res_idx++;
> + }
> +
> + ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
> + if (ret) {
> + dev_err(dev, "couldn't add res to cdns3 device\n");
> + goto free_memory;
> + }
> +
> + ret = platform_device_add(cdns3);
> + if (ret) {
> + dev_err(dev, "failed to register cdns3 device\n");
> + goto free_memory;
> + }
> +
> + return ret;
> +free_memory:
> + platform_device_put(cdns3);
> + return ret;
> +}
> +
> +static int cdns_starfive_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cdns_starfive *data;
> + unsigned int args;
> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, data);
> +
> + data->dev = dev;
> +
> + data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
> + "starfive,stg-syscon", 1, &args);
> +
> + if (IS_ERR(data->stg_syscon))
> + return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
> + "Failed to parse starfive,stg-syscon\n");
> +
> + data->stg_usb_mode = args;
> +
> + cdns_mode_init(pdev, data);
> +
> + ret = cdns_clk_rst_init(data);
> + if (ret)
> + return ret;
> +
> + data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
> + if (IS_ERR(data->usb2_phy))
> + return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
> + "Failed to parse usb2 phy\n");
> +
> + data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
> + if (IS_ERR(data->usb3_phy))
> + return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
> + "Failed to parse usb3 phy\n");
> +
You may not change the comment for if above functions are failed, there
is not opposite functions for clk and reset.
Others are okay for me.
Peter
> + cdns3_starfive_phy_init(dev, data);
> +
> + ret = cdns3_starfive_platform_device_add(pdev, data);
> + if (ret) {
> + set_phy_power_off(data);
> + phy_exit(data->usb3_phy);
> + phy_exit(data->usb2_phy);
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + return dev_err_probe(dev, ret, "Failed to create children\n");
> + }
> +
> + device_set_wakeup_capable(dev, true);
> + pm_runtime_set_active(dev);
> + pm_runtime_enable(dev);
> +
> + dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
> +
> + return 0;
> +}
> +
> +static int cdns_starfive_remove_core(struct device *dev, void *c)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> +
> + platform_device_unregister(pdev);
> +
> + return 0;
> +}
> +
> +static int cdns_starfive_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> +
> + pm_runtime_get_sync(dev);
> + device_for_each_child(dev, NULL, cdns_starfive_remove_core);
> +
> + set_phy_power_off(data);
> + phy_exit(data->usb2_phy);
> + phy_exit(data->usb3_phy);
> +
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> + pm_runtime_disable(dev);
> + pm_runtime_put_noidle(dev);
> + platform_set_drvdata(pdev, NULL);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int cdns_starfive_resume(struct device *dev)
> +{
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
> + if (ret)
> + return ret;
> +
> + ret = reset_control_deassert(data->resets);
> + if (ret)
> + return ret;
> +
> + ret = cdns3_starfive_phy_init(dev, data);
> +
> + return ret;
> +}
> +
> +static int cdns_starfive_suspend(struct device *dev)
> +{
> + struct cdns_starfive *data = dev_get_drvdata(dev);
> +
> + set_phy_power_off(data);
> + phy_exit(data->usb2_phy);
> + phy_exit(data->usb3_phy);
> + reset_control_assert(data->resets);
> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
> +
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops cdns_starfive_pm_ops = {
> + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
> + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
> +};
> +
> +static const struct of_device_id cdns_starfive_of_match[] = {
> + { .compatible = "starfive,jh7110-usb", },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
> +
> +static struct platform_driver cdns_starfive_driver = {
> + .probe = cdns_starfive_probe,
> + .remove = cdns_starfive_remove,
> + .driver = {
> + .name = "cdns3-starfive",
> + .of_match_table = cdns_starfive_of_match,
> + .pm = &cdns_starfive_pm_ops,
> + },
> +};
> +module_platform_driver(cdns_starfive_driver);
> +
> +MODULE_ALIAS("platform:cdns3-starfive");
> +MODULE_AUTHOR("YanHong Wang <yanhong.wang@starfivetech.com>");
> +MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
> diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
> index 2d332a788871..8d44ab504898 100644
> --- a/drivers/usb/cdns3/core.h
> +++ b/drivers/usb/cdns3/core.h
> @@ -38,6 +38,9 @@ struct cdns_role_driver {
> };
>
> #define CDNS_XHCI_RESOURCES_NUM 2
> +#define CDNS_IOMEM_RESOURCES_NUM 3
> +#define CDNS_IRQ_RESOURCES_NUM 4
> +#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
>
> struct cdns3_platform_data {
> int (*platform_suspend)(struct device *dev,
> --
> 2.17.1
>
--
Thanks,
Peter Chen
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver.
2023-04-11 1:01 ` Peter Chen
@ 2023-04-12 6:14 ` Minda Chen
0 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-12 6:14 UTC (permalink / raw)
To: Peter Chen
Cc: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Roger Quadros, Philipp Zabel,
devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 2023/4/11 9:01, Peter Chen wrote:
> On 23-04-06 09:52:15, Minda Chen wrote:
>> Adds Specific Glue layer to support USB peripherals on
>> StarFive JH7110 SoC.
>> There is a Cadence USB3 core for JH7110 SoCs, the cdns
>> core is the child of this USB wrapper module device.
>>
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>> MAINTAINERS | 7 +
>> drivers/usb/cdns3/Kconfig | 11 +
>> drivers/usb/cdns3/Makefile | 1 +
>> drivers/usb/cdns3/cdns3-starfive.c | 378 +++++++++++++++++++++++++++++
>> drivers/usb/cdns3/core.h | 3 +
>> 5 files changed, 400 insertions(+)
>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index d98b70d62fd4..0610bbf921bb 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -19977,6 +19977,13 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> F: drivers/phy/starfive/phy-jh7110-pcie.c
>> F: drivers/phy/starfive/phy-jh7110-usb.c
>>
>> +STARFIVE JH71X0 USB DRIVERS
>> +M: Emil Renner Berthing <kernel@esmil.dk>
>> +M: Minda Chen <minda.chen@starfivetech.com>
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> +F: drivers/usb/cdns3/cdns3-starfive.c
>> +
>> STATIC BRANCH/CALL
>> M: Peter Zijlstra <peterz@infradead.org>
>> M: Josh Poimboeuf <jpoimboe@kernel.org>
>> diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
>> index b98ca0a1352a..0a514b591527 100644
>> --- a/drivers/usb/cdns3/Kconfig
>> +++ b/drivers/usb/cdns3/Kconfig
>> @@ -78,6 +78,17 @@ config USB_CDNS3_IMX
>>
>> For example, imx8qm and imx8qxp.
>>
>> +config USB_CDNS3_STARFIVE
>> + tristate "Cadence USB3 support on StarFive SoC platforms"
>> + depends on ARCH_STARFIVE || COMPILE_TEST
>> + help
>> + Say 'Y' or 'M' here if you are building for StarFive SoCs
>> + platforms that contain Cadence USB3 controller core.
>> +
>> + e.g. JH7110.
>> +
>> + If you choose to build this driver as module it will
>> + be dynamically linked and module will be called cdns3-starfive.ko
>> endif
>>
>> if USB_CDNS_SUPPORT
>> diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
>> index 61edb2f89276..48dfae75b5aa 100644
>> --- a/drivers/usb/cdns3/Makefile
>> +++ b/drivers/usb/cdns3/Makefile
>> @@ -24,6 +24,7 @@ endif
>> obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o
>> obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
>> obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o
>> +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o
>>
>> cdnsp-udc-pci-y := cdnsp-pci.o
>>
>> diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
>> new file mode 100644
>> index 000000000000..925209a97bf9
>> --- /dev/null
>> +++ b/drivers/usb/cdns3/cdns3-starfive.c
>> @@ -0,0 +1,378 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/**
>> + * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
>> + *
>> + * Copyright (C) 2022 Starfive, Inc.
>> + * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
>> + * Author: Mason Huo <mason.huo@starfivetech.com>
>> + * Author: Minda Chen <minda.chen@starfivetech.com>
>> + */
>> +
>> +#include <linux/bits.h>
>> +#include <linux/clk.h>
>> +#include <linux/module.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/kernel.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/io.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/regmap.h>
>> +#include <linux/reset.h>
>> +#include <linux/usb/otg.h>
>> +#include "core.h"
>> +
>> +#define USB_STRAP_HOST BIT(17)
>> +#define USB_STRAP_DEVICE BIT(18)
>> +#define USB_STRAP_MASK GENMASK(18, 16)
>> +
>> +#define USB_SUSPENDM_HOST BIT(19)
>> +#define USB_SUSPENDM_MASK BIT(19)
>> +#define CDNS_IRQ_WAKEUP_INDEX 3
>> +
>> +struct cdns_starfive {
>> + struct device *dev;
>> + struct phy *usb2_phy;
>> + struct phy *usb3_phy;
>> + struct regmap *stg_syscon;
>> + struct reset_control *resets;
>> + struct clk_bulk_data *clks;
>> + int num_clks;
>> + enum phy_mode phy_mode;
>> + u32 stg_usb_mode;
>> +};
>> +
>> +static int set_phy_power_on(struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + ret = phy_power_on(data->usb2_phy);
>> + if (ret)
>> + return ret;
>> +
>> + ret = phy_power_on(data->usb3_phy);
>> + if (ret)
>> + phy_power_off(data->usb2_phy);
>> +
>> + return ret;
>> +}
>> +
>> +static void set_phy_power_off(struct cdns_starfive *data)
>> +{
>> + phy_power_off(data->usb3_phy);
>> + phy_power_off(data->usb2_phy);
>> +}
>> +
>> +static void cdns_mode_init(struct platform_device *pdev,
>> + struct cdns_starfive *data)
>> +{
>> + enum usb_dr_mode mode;
>> +
>> + mode = usb_get_dr_mode(&pdev->dev);
>> +
>> + switch (mode) {
>> + case USB_DR_MODE_HOST:
>> + regmap_update_bits(data->stg_syscon,
>> + data->stg_usb_mode,
>> + USB_STRAP_MASK,
>> + USB_STRAP_HOST);
>> + regmap_update_bits(data->stg_syscon,
>> + data->stg_usb_mode,
>> + USB_SUSPENDM_MASK,
>> + USB_SUSPENDM_HOST);
>> + data->phy_mode = PHY_MODE_USB_HOST;
>> + break;
>> +
>> + case USB_DR_MODE_PERIPHERAL:
>> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
>> + USB_STRAP_MASK, USB_STRAP_DEVICE);
>> + regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
>> + USB_SUSPENDM_MASK, 0);
>> + data->phy_mode = PHY_MODE_USB_DEVICE;
>> + break;
>> +
>> + case USB_DR_MODE_OTG:
>> + data->phy_mode = PHY_MODE_USB_OTG;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +static int cdns_clk_rst_init(struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
>> + if (data->num_clks < 0)
>> + return dev_err_probe(data->dev, -ENODEV,
>> + "Failed to get clocks\n");
>> +
>> + data->resets = devm_reset_control_array_get_exclusive(data->dev);
>> + if (IS_ERR(data->resets)) {
>> + return dev_err_probe(data->dev, PTR_ERR(data->resets),
>> + "Failed to get resets");
>> + }
>> +
>> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
>> + if (ret)
>> + return dev_err_probe(data->dev, ret,
>> + "failed to enable clocks\n");
>> +
>> + ret = reset_control_deassert(data->resets);
>> + if (ret) {
>> + ret = dev_err_probe(data->dev, ret,
>> + "failed to reset clocks\n");
>> + goto err_clk_init;
>> + }
>> +
>> + return ret;
>> +
>> +err_clk_init:
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + return ret;
>> +}
>> +
>> +static int cdns3_starfive_phy_init(struct device *dev, struct cdns_starfive *data)
>> +{
>> + int ret;
>> +
>> + ret = phy_init(data->usb2_phy);
>> + if (ret)
>> + return ret;
>> +
>> + ret = phy_init(data->usb3_phy);
>> + if (ret)
>> + goto err_phy3_init;
>> +
>> + ret = set_phy_power_on(data);
>> + if (ret)
>> + goto err_phy_power_on;
>> +
>> + phy_set_mode(data->usb2_phy, data->phy_mode);
>> + phy_set_mode(data->usb3_phy, data->phy_mode);
>> +
>> + return 0;
>> +
>> +err_phy_power_on:
>> + phy_exit(data->usb3_phy);
>> +err_phy3_init:
>> + phy_exit(data->usb2_phy);
>> + return ret;
>> +}
>> +
>> +static int cdns3_starfive_platform_device_add(struct platform_device *pdev,
>> + struct cdns_starfive *data)
>> +{
>> + struct platform_device *cdns3;
>> + struct resource cdns_res[CDNS_RESOURCES_NUM], *res;
>> + struct device *dev = &pdev->dev;
>> + const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"};
>> + const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"};
>> + int i, ret, res_idx = 0;
>> +
>> + cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO);
>> + if (!cdns3)
>> + return dev_err_probe(dev, -ENOMEM,
>> + "couldn't alloc cdns3 usb device\n");
>> +
>> + cdns3->dev.parent = dev;
>> + memset(cdns_res, 0, sizeof(cdns_res));
>> +
>> + for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) {
>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]);
>> + if (!res) {
>> + ret = dev_err_probe(dev,
>> + -ENXIO, "couldn't get %s reg resource\n", reg_name[i]);
>> + goto free_memory;
>> + }
>> + cdns_res[res_idx] = *res;
>> + res_idx++;
>> + }
>> +
>> + for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) {
>> + if (i == CDNS_IRQ_WAKEUP_INDEX) {
>> + ret = platform_get_irq_byname_optional(pdev, irq_name[i]);
>> + if (ret < 0)
>> + continue;
>> + } else {
>> + ret = platform_get_irq_byname(pdev, irq_name[i]);
>> + if (ret < 0) {
>> + dev_err(dev, "couldn't get %s irq\n", irq_name[i]);
>> + goto free_memory;
>> + }
>> + }
>> + cdns_res[res_idx].start = ret;
>> + cdns_res[res_idx].end = ret;
>> + cdns_res[res_idx].flags = IORESOURCE_IRQ;
>> + cdns_res[res_idx].name = irq_name[i];
>> + res_idx++;
>> + }
>> +
>> + ret = platform_device_add_resources(cdns3, cdns_res, res_idx);
>> + if (ret) {
>> + dev_err(dev, "couldn't add res to cdns3 device\n");
>> + goto free_memory;
>> + }
>> +
>> + ret = platform_device_add(cdns3);
>> + if (ret) {
>> + dev_err(dev, "failed to register cdns3 device\n");
>> + goto free_memory;
>> + }
>> +
>> + return ret;
>> +free_memory:
>> + platform_device_put(cdns3);
>> + return ret;
>> +}
>> +
>> +static int cdns_starfive_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cdns_starfive *data;
>> + unsigned int args;
>> + int ret;
>> +
>> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, data);
>> +
>> + data->dev = dev;
>> +
>> + data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
>> + "starfive,stg-syscon", 1, &args);
>> +
>> + if (IS_ERR(data->stg_syscon))
>> + return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
>> + "Failed to parse starfive,stg-syscon\n");
>> +
>> + data->stg_usb_mode = args;
>> +
>> + cdns_mode_init(pdev, data);
>> +
>> + ret = cdns_clk_rst_init(data);
>> + if (ret)
>> + return ret;
>> +
>> + data->usb2_phy = devm_phy_optional_get(dev, "usb2-phy");
>> + if (IS_ERR(data->usb2_phy))
>> + return dev_err_probe(dev, PTR_ERR(data->usb2_phy),
>> + "Failed to parse usb2 phy\n");
>> +
>> + data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
>> + if (IS_ERR(data->usb3_phy))
>> + return dev_err_probe(dev, PTR_ERR(data->usb3_phy),
>> + "Failed to parse usb3 phy\n");
>> +
>
> You may not change the comment for if above functions are failed, there
> is not opposite functions for clk and reset.
>
> Others are okay for me.
>
> Peter
>
OK, I will change this. Thank you very much.
>> + cdns3_starfive_phy_init(dev, data);
>> +
>> + ret = cdns3_starfive_platform_device_add(pdev, data);
>> + if (ret) {
>> + set_phy_power_off(data);
>> + phy_exit(data->usb3_phy);
>> + phy_exit(data->usb2_phy);
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + return dev_err_probe(dev, ret, "Failed to create children\n");
>> + }
>> +
>> + device_set_wakeup_capable(dev, true);
>> + pm_runtime_set_active(dev);
>> + pm_runtime_enable(dev);
>> +
>> + dev_info(dev, "usb mode %d probe success\n", data->phy_mode);
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_starfive_remove_core(struct device *dev, void *c)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> +
>> + platform_device_unregister(pdev);
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_starfive_remove(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> +
>> + pm_runtime_get_sync(dev);
>> + device_for_each_child(dev, NULL, cdns_starfive_remove_core);
>> +
>> + set_phy_power_off(data);
>> + phy_exit(data->usb2_phy);
>> + phy_exit(data->usb3_phy);
>> +
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> + pm_runtime_disable(dev);
>> + pm_runtime_put_noidle(dev);
>> + platform_set_drvdata(pdev, NULL);
>> +
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int cdns_starfive_resume(struct device *dev)
>> +{
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
>> + if (ret)
>> + return ret;
>> +
>> + ret = reset_control_deassert(data->resets);
>> + if (ret)
>> + return ret;
>> +
>> + ret = cdns3_starfive_phy_init(dev, data);
>> +
>> + return ret;
>> +}
>> +
>> +static int cdns_starfive_suspend(struct device *dev)
>> +{
>> + struct cdns_starfive *data = dev_get_drvdata(dev);
>> +
>> + set_phy_power_off(data);
>> + phy_exit(data->usb2_phy);
>> + phy_exit(data->usb3_phy);
>> + reset_control_assert(data->resets);
>> + clk_bulk_disable_unprepare(data->num_clks, data->clks);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static const struct dev_pm_ops cdns_starfive_pm_ops = {
>> + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
>> + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
>> +};
>> +
>> +static const struct of_device_id cdns_starfive_of_match[] = {
>> + { .compatible = "starfive,jh7110-usb", },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
>> +
>> +static struct platform_driver cdns_starfive_driver = {
>> + .probe = cdns_starfive_probe,
>> + .remove = cdns_starfive_remove,
>> + .driver = {
>> + .name = "cdns3-starfive",
>> + .of_match_table = cdns_starfive_of_match,
>> + .pm = &cdns_starfive_pm_ops,
>> + },
>> +};
>> +module_platform_driver(cdns_starfive_driver);
>> +
>> +MODULE_ALIAS("platform:cdns3-starfive");
>> +MODULE_AUTHOR("YanHong Wang <yanhong.wang@starfivetech.com>");
>> +MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
>> diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
>> index 2d332a788871..8d44ab504898 100644
>> --- a/drivers/usb/cdns3/core.h
>> +++ b/drivers/usb/cdns3/core.h
>> @@ -38,6 +38,9 @@ struct cdns_role_driver {
>> };
>>
>> #define CDNS_XHCI_RESOURCES_NUM 2
>> +#define CDNS_IOMEM_RESOURCES_NUM 3
>> +#define CDNS_IRQ_RESOURCES_NUM 4
>> +#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM)
>>
>> struct cdns3_platform_data {
>> int (*platform_suspend)(struct device *dev,
>> --
>> 2.17.1
>>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 7/7] riscv: dts: starfive: add USB dts configuration for JH7110
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
` (5 preceding siblings ...)
2023-04-06 1:52 ` [PATCH v4 6/7] usb: cdns3: add StarFive JH7110 USB driver Minda Chen
@ 2023-04-06 1:52 ` Minda Chen
2023-04-12 8:26 ` [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Krzysztof Kozlowski
7 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-06 1:52 UTC (permalink / raw)
To: Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Minda Chen, Mason Huo
Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.
USB controller connect to PHY, The PHY dts configuration
are also added.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
.../jh7110-starfive-visionfive-2.dtsi | 7 +++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 +++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 1155b97b593d..cf0a66faf5d3 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -221,3 +221,10 @@
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
+
+&usb0 {
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ dr_mode = "peripheral";
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 29cd798b6732..2f67196ffac0 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -366,6 +366,50 @@
status = "disabled";
};
+ usb0: usb@10100000 {
+ compatible = "starfive,jh7110-usb";
+ reg = <0x0 0x10100000 0x0 0x10000>,
+ <0x0 0x10110000 0x0 0x10000>,
+ <0x0 0x10120000 0x0 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <100>, <108>, <110>;
+ interrupt-names = "host", "peripheral", "otg";
+ clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
+ <&stgcrg JH7110_STGCLK_USB0_STB>,
+ <&stgcrg JH7110_STGCLK_USB0_APB>,
+ <&stgcrg JH7110_STGCLK_USB0_AXI>,
+ <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+ resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
+ <&stgcrg JH7110_STGRST_USB0_APB>,
+ <&stgcrg JH7110_STGRST_USB0_AXI>,
+ <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
+ reset-names = "pwrup","apb","axi","utmi";
+ starfive,stg-syscon = <&stg_syscon 0x4>;
+ status = "disabled";
+ };
+
+ usbphy0: phy@10200000 {
+ compatible = "starfive,jh7110-usb-phy";
+ reg = <0x0 0x10200000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+ <&stgcrg JH7110_STGCLK_USB0_APP_125>;
+ clock-names = "125m", "app_125";
+ #phy-cells = <0>;
+ };
+
+ pciephy0: phy@10210000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10210000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
+ pciephy1: phy@10220000 {
+ compatible = "starfive,jh7110-pcie-phy";
+ reg = <0x0 0x10220000 0x0 0x10000>;
+ #phy-cells = <0>;
+ };
+
stgcrg: clock-controller@10230000 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x10230000 0x0 0x10000>;
--
2.17.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-06 1:52 [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Minda Chen
` (6 preceding siblings ...)
2023-04-06 1:52 ` [PATCH v4 7/7] riscv: dts: starfive: add USB dts configuration for JH7110 Minda Chen
@ 2023-04-12 8:26 ` Krzysztof Kozlowski
2023-04-13 10:44 ` Minda Chen
7 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-12 8:26 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 06/04/2023 03:52, Minda Chen wrote:
> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
> The patch has been tested on the VisionFive 2 board.
>
> This patchset should be applied after the patchset [1], [2] and[3]:
> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230314124404.117592-1-xingyu.wu@starfivetech.com/
> [2] https://lore.kernel.org/all/20230315055813.94740-1-william.qiu@starfivetech.com/
> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230315100421.133428-1-changhuang.liang@starfivetech.com/
>
> This patchset is base on v6.3-rc4
>
> patch 1 is usb phy dt-binding document.
> patch 2 is Pcie PHY dt-binding document.
> patch 3 is USB 2.0 PHY driver.
> patch 4 is PCIe PHY driver.
> patch 5 is usb dt-binding document.
> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
> patch 7 is USB device tree configuration.
>
> previous version
> ---
> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
This is v2.
> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
>
> changes
> v4:
> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
> 3. (patch 3)
> - split PCIe PHY driver to patch 4.
> - replace dr_mode to phy mode in jh7110_usb2_phy.
> 4. (patch 4)
> - Makefile and Kconfig sorted by alphabet sequence.
> - Add PCIe PHY stg and syscon PHY connection configuration
> for USB 3.0.
> 5. (patch 5)
> - commit message changed.
> - merge wrapper dts node and cdns3 node in example.
> - Add interrupts, reg, phy and dr_mode in property.
> - Add reset-name in property example.
> 6. (patch 6)
> - For dts node is merged, Using platform_device_alloc and
> platform_device_add to generate cadence sub device.
> - IOMEM and IRQ resource are passed to Cadence sub device.
> - Add PHY ops process for PHY dts setting can not be passed to
> Cadence USB driver.
> - remove the stg and sys USB 3.0 PHY configuration.
> - Change the suspend clock reset and clock enable sequence.
> - Get all reset and clock resources before enable them in
> cdns_clk_rst_init.
> - commit message changed.
> 7. (patch 7)
> - merge wrapper dts node and cdns3 node in usb dts.
> - move the stg and sys USB 3.0 PHY confiuration to
> PCIe PHY dts node.
> - commit message changed.
> - Add reset-names dts.
>
> v3:
> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
> USB PHY codes are moved to patch 3 and patch 4.
> 2. (patch 5)
> - USB wrapper module dts document is moved to usb directory.
> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
> - Some dts format changes. dts binding check pass.
> 3. (patch 6)
> - Remove the PHY codes.
> - Search 'dr_mode' and phy setting from Cadence subnode.
> 4. (patch 7)
> - Add USB PHY dts configurion.
> - 'dr_mode' is moved to Cadence controller submode.
>
> v2:
> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
> 3. (patch 7) dts nodes sorted by the address after @
>
>
> Minda Chen (7):
> dt-bindings: phy: Add StarFive JH7110 USB document
> dt-bindings: phy: Add StarFive JH7110 PCIe document
> phy: starfive: add JH7110 USB 2.0 PHY driver.
> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
> usb: cdns3: add StarFive JH7110 USB driver.
> riscv: dts: starfive: add USB dts configuration for JH7110
>
> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
> MAINTAINERS | 16 +
> .../jh7110-starfive-visionfive-2.dtsi | 7 +
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
> drivers/phy/starfive/Kconfig | 22 +
> drivers/phy/starfive/Makefile | 2 +
> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
> drivers/usb/cdns3/Kconfig | 11 +
> drivers/usb/cdns3/Makefile | 1 +
> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
> drivers/usb/cdns3/core.h | 3 +
> 14 files changed, 1086 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>
>
> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
What commits do you reference? How are they helpful?
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-12 8:26 ` [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support Krzysztof Kozlowski
@ 2023-04-13 10:44 ` Minda Chen
2023-04-13 14:13 ` Krzysztof Kozlowski
0 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-13 10:44 UTC (permalink / raw)
To: Krzysztof Kozlowski, Emil Renner Berthing, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Pawel Laszczak, Greg Kroah-Hartman,
Peter Chen, Roger Quadros, Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
> On 06/04/2023 03:52, Minda Chen wrote:
>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>> The patch has been tested on the VisionFive 2 board.
>>
>> This patchset should be applied after the patchset [1], [2] and[3]:
>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230314124404.117592-1-xingyu.wu@starfivetech.com/
>> [2] https://lore.kernel.org/all/20230315055813.94740-1-william.qiu@starfivetech.com/
>> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230315100421.133428-1-changhuang.liang@starfivetech.com/
>>
>> This patchset is base on v6.3-rc4
>>
>> patch 1 is usb phy dt-binding document.
>> patch 2 is Pcie PHY dt-binding document.
>> patch 3 is USB 2.0 PHY driver.
>> patch 4 is PCIe PHY driver.
>> patch 5 is usb dt-binding document.
>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>> patch 7 is USB device tree configuration.
>>
>> previous version
>> ---
>> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
>> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
>
> This is v2.
>
>> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
>>
>> changes
>> v4:
>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>> 3. (patch 3)
>> - split PCIe PHY driver to patch 4.
>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>> 4. (patch 4)
>> - Makefile and Kconfig sorted by alphabet sequence.
>> - Add PCIe PHY stg and syscon PHY connection configuration
>> for USB 3.0.
>> 5. (patch 5)
>> - commit message changed.
>> - merge wrapper dts node and cdns3 node in example.
>> - Add interrupts, reg, phy and dr_mode in property.
>> - Add reset-name in property example.
>> 6. (patch 6)
>> - For dts node is merged, Using platform_device_alloc and
>> platform_device_add to generate cadence sub device.
>> - IOMEM and IRQ resource are passed to Cadence sub device.
>> - Add PHY ops process for PHY dts setting can not be passed to
>> Cadence USB driver.
>> - remove the stg and sys USB 3.0 PHY configuration.
>> - Change the suspend clock reset and clock enable sequence.
>> - Get all reset and clock resources before enable them in
>> cdns_clk_rst_init.
>> - commit message changed.
>> 7. (patch 7)
>> - merge wrapper dts node and cdns3 node in usb dts.
>> - move the stg and sys USB 3.0 PHY confiuration to
>> PCIe PHY dts node.
>> - commit message changed.
>> - Add reset-names dts.
>>
>> v3:
>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>> USB PHY codes are moved to patch 3 and patch 4.
>> 2. (patch 5)
>> - USB wrapper module dts document is moved to usb directory.
>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>> - Some dts format changes. dts binding check pass.
>> 3. (patch 6)
>> - Remove the PHY codes.
>> - Search 'dr_mode' and phy setting from Cadence subnode.
>> 4. (patch 7)
>> - Add USB PHY dts configurion.
>> - 'dr_mode' is moved to Cadence controller submode.
>>
>> v2:
>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>> 3. (patch 7) dts nodes sorted by the address after @
>>
>>
>> Minda Chen (7):
>> dt-bindings: phy: Add StarFive JH7110 USB document
>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>> usb: cdns3: add StarFive JH7110 USB driver.
>> riscv: dts: starfive: add USB dts configuration for JH7110
>>
>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>> MAINTAINERS | 16 +
>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>> drivers/phy/starfive/Kconfig | 22 +
>> drivers/phy/starfive/Makefile | 2 +
>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>> drivers/usb/cdns3/Kconfig | 11 +
>> drivers/usb/cdns3/Makefile | 1 +
>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>> drivers/usb/cdns3/core.h | 3 +
>> 14 files changed, 1086 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>
>>
>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>
> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>
> What commits do you reference? How are they helpful?
>
I use "git format-patch --base=(commit) to generate patchset.
Maybe I set the wrong base commit.
>
> Best regards,
> Krzysztof
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-13 10:44 ` Minda Chen
@ 2023-04-13 14:13 ` Krzysztof Kozlowski
2023-04-18 11:12 ` Minda Chen
0 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-13 14:13 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 13/04/2023 12:44, Minda Chen wrote:
>
>
> On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
>> On 06/04/2023 03:52, Minda Chen wrote:
>>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>>> The patch has been tested on the VisionFive 2 board.
>>>
>>> This patchset should be applied after the patchset [1], [2] and[3]:
>>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230314124404.117592-1-xingyu.wu@starfivetech.com/
>>> [2] https://lore.kernel.org/all/20230315055813.94740-1-william.qiu@starfivetech.com/
>>> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230315100421.133428-1-changhuang.liang@starfivetech.com/
>>>
>>> This patchset is base on v6.3-rc4
>>>
>>> patch 1 is usb phy dt-binding document.
>>> patch 2 is Pcie PHY dt-binding document.
>>> patch 3 is USB 2.0 PHY driver.
>>> patch 4 is PCIe PHY driver.
>>> patch 5 is usb dt-binding document.
>>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>>> patch 7 is USB device tree configuration.
>>>
>>> previous version
>>> ---
>>> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
>>> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
>>
>> This is v2.
>>
>>> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
>>>
>>> changes
>>> v4:
>>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>>> 3. (patch 3)
>>> - split PCIe PHY driver to patch 4.
>>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>>> 4. (patch 4)
>>> - Makefile and Kconfig sorted by alphabet sequence.
>>> - Add PCIe PHY stg and syscon PHY connection configuration
>>> for USB 3.0.
>>> 5. (patch 5)
>>> - commit message changed.
>>> - merge wrapper dts node and cdns3 node in example.
>>> - Add interrupts, reg, phy and dr_mode in property.
>>> - Add reset-name in property example.
>>> 6. (patch 6)
>>> - For dts node is merged, Using platform_device_alloc and
>>> platform_device_add to generate cadence sub device.
>>> - IOMEM and IRQ resource are passed to Cadence sub device.
>>> - Add PHY ops process for PHY dts setting can not be passed to
>>> Cadence USB driver.
>>> - remove the stg and sys USB 3.0 PHY configuration.
>>> - Change the suspend clock reset and clock enable sequence.
>>> - Get all reset and clock resources before enable them in
>>> cdns_clk_rst_init.
>>> - commit message changed.
>>> 7. (patch 7)
>>> - merge wrapper dts node and cdns3 node in usb dts.
>>> - move the stg and sys USB 3.0 PHY confiuration to
>>> PCIe PHY dts node.
>>> - commit message changed.
>>> - Add reset-names dts.
>>>
>>> v3:
>>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>>> USB PHY codes are moved to patch 3 and patch 4.
>>> 2. (patch 5)
>>> - USB wrapper module dts document is moved to usb directory.
>>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>>> - Some dts format changes. dts binding check pass.
>>> 3. (patch 6)
>>> - Remove the PHY codes.
>>> - Search 'dr_mode' and phy setting from Cadence subnode.
>>> 4. (patch 7)
>>> - Add USB PHY dts configurion.
>>> - 'dr_mode' is moved to Cadence controller submode.
>>>
>>> v2:
>>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>>> 3. (patch 7) dts nodes sorted by the address after @
>>>
>>>
>>> Minda Chen (7):
>>> dt-bindings: phy: Add StarFive JH7110 USB document
>>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>>> usb: cdns3: add StarFive JH7110 USB driver.
>>> riscv: dts: starfive: add USB dts configuration for JH7110
>>>
>>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>>> MAINTAINERS | 16 +
>>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>>> drivers/phy/starfive/Kconfig | 22 +
>>> drivers/phy/starfive/Makefile | 2 +
>>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>>> drivers/usb/cdns3/Kconfig | 11 +
>>> drivers/usb/cdns3/Makefile | 1 +
>>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>>> drivers/usb/cdns3/core.h | 3 +
>>> 14 files changed, 1086 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>>
>>>
>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>
>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>
>> What commits do you reference? How are they helpful?
>>
> I use "git format-patch --base=(commit) to generate patchset.
> Maybe I set the wrong base commit.
How are they helpful if these are private commits?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-13 14:13 ` Krzysztof Kozlowski
@ 2023-04-18 11:12 ` Minda Chen
2023-04-18 12:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 20+ messages in thread
From: Minda Chen @ 2023-04-18 11:12 UTC (permalink / raw)
To: Krzysztof Kozlowski, Emil Renner Berthing, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski, Pawel Laszczak, Greg Kroah-Hartman,
Peter Chen, Roger Quadros, Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 2023/4/13 22:13, Krzysztof Kozlowski wrote:
> On 13/04/2023 12:44, Minda Chen wrote:
>>
>>
>> On 2023/4/12 16:26, Krzysztof Kozlowski wrote:
>>> On 06/04/2023 03:52, Minda Chen wrote:
>>>> This patchset adds USB driver and USB PHY for the StarFive JH7110 SoC.
>>>> USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
>>>> The patch has been tested on the VisionFive 2 board.
>>>>
>>>> This patchset should be applied after the patchset [1], [2] and[3]:
>>>> [1] https://patchwork.kernel.org/project/linux-riscv/cover/20230314124404.117592-1-xingyu.wu@starfivetech.com/
>>>> [2] https://lore.kernel.org/all/20230315055813.94740-1-william.qiu@starfivetech.com/
>>>> [3] https://patchwork.kernel.org/project/linux-phy/cover/20230315100421.133428-1-changhuang.liang@starfivetech.com/
>>>>
>>>> This patchset is base on v6.3-rc4
>>>>
>>>> patch 1 is usb phy dt-binding document.
>>>> patch 2 is Pcie PHY dt-binding document.
>>>> patch 3 is USB 2.0 PHY driver.
>>>> patch 4 is PCIe PHY driver.
>>>> patch 5 is usb dt-binding document.
>>>> patch 6 is the wrapper module driver of Cadence USB3. USB controller IP is Cadence USB3.
>>>> patch 7 is USB device tree configuration.
>>>>
>>>> previous version
>>>> ---
>>>> v1: https://patchwork.kernel.org/project/linux-usb/cover/20230306095212.25840-1-minda.chen@starfivetech.com/
>>>> v2: https://patchwork.kernel.org/project/linux-usb/cover/20230308082800.3008-1-minda.chen@starfivetech.com/
>>>
>>> This is v2.
>>>
>>>> v3: https://patchwork.kernel.org/project/linux-usb/cover/20230315104411.73614-1-minda.chen@starfivetech.com/
>>>>
>>>> changes
>>>> v4:
>>>> 1. (patch 1) split PCIe PHY dt-binding doc to patch 2.
>>>> 2. (patch 2) PCIe PHY add stg and sys con configuration to dt-binding doc.
>>>> 3. (patch 3)
>>>> - split PCIe PHY driver to patch 4.
>>>> - replace dr_mode to phy mode in jh7110_usb2_phy.
>>>> 4. (patch 4)
>>>> - Makefile and Kconfig sorted by alphabet sequence.
>>>> - Add PCIe PHY stg and syscon PHY connection configuration
>>>> for USB 3.0.
>>>> 5. (patch 5)
>>>> - commit message changed.
>>>> - merge wrapper dts node and cdns3 node in example.
>>>> - Add interrupts, reg, phy and dr_mode in property.
>>>> - Add reset-name in property example.
>>>> 6. (patch 6)
>>>> - For dts node is merged, Using platform_device_alloc and
>>>> platform_device_add to generate cadence sub device.
>>>> - IOMEM and IRQ resource are passed to Cadence sub device.
>>>> - Add PHY ops process for PHY dts setting can not be passed to
>>>> Cadence USB driver.
>>>> - remove the stg and sys USB 3.0 PHY configuration.
>>>> - Change the suspend clock reset and clock enable sequence.
>>>> - Get all reset and clock resources before enable them in
>>>> cdns_clk_rst_init.
>>>> - commit message changed.
>>>> 7. (patch 7)
>>>> - merge wrapper dts node and cdns3 node in usb dts.
>>>> - move the stg and sys USB 3.0 PHY confiuration to
>>>> PCIe PHY dts node.
>>>> - commit message changed.
>>>> - Add reset-names dts.
>>>>
>>>> v3:
>>>> 1. Add patch 1 - 4. Add USB PHY driver and dt-binding doc.
>>>> USB PHY codes are moved to patch 3 and patch 4.
>>>> 2. (patch 5)
>>>> - USB wrapper module dts document is moved to usb directory.
>>>> - Remove the 'dr_mode' and 'starfive,usb2-only' setting.
>>>> - Some dts format changes. dts binding check pass.
>>>> 3. (patch 6)
>>>> - Remove the PHY codes.
>>>> - Search 'dr_mode' and phy setting from Cadence subnode.
>>>> 4. (patch 7)
>>>> - Add USB PHY dts configurion.
>>>> - 'dr_mode' is moved to Cadence controller submode.
>>>>
>>>> v2:
>>>> 1. (patch 5) dt-binding changes. The document example is the same as dts config.
>>>> 2. (patch 6) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
>>>> 3. (patch 7) dts nodes sorted by the address after @
>>>>
>>>>
>>>> Minda Chen (7):
>>>> dt-bindings: phy: Add StarFive JH7110 USB document
>>>> dt-bindings: phy: Add StarFive JH7110 PCIe document
>>>> phy: starfive: add JH7110 USB 2.0 PHY driver.
>>>> phy: starfive: add JH7110 PCIE 2.0 PHY driver.
>>>> dt-bindings: usb: Add StarFive JH7110 USB Bindings YAML schemas
>>>> usb: cdns3: add StarFive JH7110 USB driver.
>>>> riscv: dts: starfive: add USB dts configuration for JH7110
>>>>
>>>> .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++
>>>> .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++
>>>> .../bindings/usb/starfive,jh7110-usb.yaml | 136 +++++++
>>>> MAINTAINERS | 16 +
>>>> .../jh7110-starfive-visionfive-2.dtsi | 7 +
>>>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 ++
>>>> drivers/phy/starfive/Kconfig | 22 +
>>>> drivers/phy/starfive/Makefile | 2 +
>>>> drivers/phy/starfive/phy-jh7110-pcie.c | 197 +++++++++
>>>> drivers/phy/starfive/phy-jh7110-usb.c | 161 ++++++++
>>>> drivers/usb/cdns3/Kconfig | 11 +
>>>> drivers/usb/cdns3/Makefile | 1 +
>>>> drivers/usb/cdns3/cdns3-starfive.c | 378 ++++++++++++++++++
>>>> drivers/usb/cdns3/core.h | 3 +
>>>> 14 files changed, 1086 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>>>> create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
>>>> create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
>>>> create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c
>>>> create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
>>>>
>>>>
>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>
>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>
>>> What commits do you reference? How are they helpful?
>>>
>> I use "git format-patch --base=(commit) to generate patchset.
>> Maybe I set the wrong base commit.
>
> How are they helpful if these are private commits?
>> Best regards,
> Krzysztof
>
base-commit is not private commits.
I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
_______________________________________________
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-18 11:12 ` Minda Chen
@ 2023-04-18 12:22 ` Krzysztof Kozlowski
2023-04-19 8:16 ` Minda Chen
0 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-04-18 12:22 UTC (permalink / raw)
To: Minda Chen, Emil Renner Berthing, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 18/04/2023 13:12, Minda Chen wrote:
>>>>>
>>>>>
>>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>
>>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>
>>>> What commits do you reference? How are they helpful?
>>>>
>>> I use "git format-patch --base=(commit) to generate patchset.
>>> Maybe I set the wrong base commit.
>>
>> How are they helpful if these are private commits?
>>> Best regards,
>> Krzysztof
>>
> base-commit is not private commits.
> I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
> But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
You missed the point. I am not talking about base commit. I am talking
about your prerequisites, which are useless. What can we do with such SHA?
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/7] Add JH7110 USB and USB PHY driver support
2023-04-18 12:22 ` Krzysztof Kozlowski
@ 2023-04-19 8:16 ` Minda Chen
0 siblings, 0 replies; 20+ messages in thread
From: Minda Chen @ 2023-04-19 8:16 UTC (permalink / raw)
To: Krzysztof Kozlowski, Emil Renner Berthing, Conor Dooley,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
Pawel Laszczak, Greg Kroah-Hartman, Peter Chen, Roger Quadros,
Philipp Zabel
Cc: devicetree, linux-kernel, linux-phy, linux-usb, linux-riscv,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Mason Huo
On 2023/4/18 20:22, Krzysztof Kozlowski wrote:
> On 18/04/2023 13:12, Minda Chen wrote:
>>>>>>
>>>>>>
>>>>>> base-commit: 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35
>>>>>> prerequisite-patch-id: 24a6e3442ed1f5454ffb4a514cfd768436a87090
>>>>>> prerequisite-patch-id: 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>>
>>>>> fatal: bad object 55390537360f25c8b9cbfdc30b73ade004f436f7
>>>>>
>>>>> What commits do you reference? How are they helpful?
>>>>>
>>>> I use "git format-patch --base=(commit) to generate patchset.
>>>> Maybe I set the wrong base commit.
>>>
>>> How are they helpful if these are private commits?
>>>> Best regards,
>>> Krzysztof
>>>
>> base-commit is not private commits.
>> I should set base commit 197b6b60ae7bc51dd0814953c562833143b292aa. This is 6.3-rc4 commit.
>> But I set 0ec57cfa721fbd36b4c4c0d9ccc5d78a78f7fa35. This is 6.3-rc4's previous commit.
>
> You missed the point. I am not talking about base commit. I am talking
> about your prerequisites, which are useless. What can we do with such SHA?
>
> Best regards,
> Krzysztof
>
OK， I will delete them
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^ permalink raw reply [flat|nested] 20+ messages in thread