[PATCH v1 0/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

[PATCH v1 0/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Do the various bits needed to drop the additionalProperties: true that
we currently have in riscv/cpu.yaml, to permit actually enforcing what
people put in cpus nodes.

CC: Rob Herring <robh+dt@kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
CC: Paul Walmsley <paul.walmsley@sifive.com>
CC: Palmer Dabbelt <palmer@dabbelt.com>
CC: linux-riscv@lists.infradead.org
CC: devicetree@vger.kernel.org
CC: linux-kernel@vger.kernel.org

Conor Dooley (6):
  dt-bindings: riscv: cpus: add a ref the common cpu schema
  dt-bindings: riscv: cpus: allow clocks property
  dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
  dt-bindings: riscv: cpus: permit operating-points-v2
  dt-bindings: riscv: cpus: document cpu-supply
  dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

 .../devicetree/bindings/riscv/cpus.yaml         | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

-- 
2.39.2


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[PATCH v1 1/6] dt-bindings: riscv: cpus: add a ref the common cpu schema

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

To permit validation of RISC-V cpu nodes, "additionalProperties: true"
needs to be swapped for "unevaluatedProperties: false". To facilitate
this in a way that passes dt_binding_check, a reference to the cpu
schema is required.

Disallow the generic cache-op-block-size property that that drags in,
since the RISC-V CBO extensions do not require a common size, and have
individual properties.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 3d2934b15e80..e89a10d9c06b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -23,6 +23,9 @@ description: |
   two cores, each of which has two hyperthreads, could be described as
   having four harts.
 
+allOf:
+  - $ref: /schemas/cpu.yaml#
+
 properties:
   compatible:
     oneOf:
@@ -98,6 +101,9 @@ properties:
     $ref: "/schemas/types.yaml#/definitions/string"
     pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
 
+  # RISC-V has multiple properties for cache op block sizes as the sizes
+  # differ between individual CBO extensions
+  cache-op-block-size: false
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.39.2


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[PATCH v1 2/6] dt-bindings: riscv: cpus: allow clocks property

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

Having disallowed additionalProperties, dtbs_check complains about
unevaluated clocks properties. Permit a single clock, as that's all any
current dts uses.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e89a10d9c06b..3808a6703b2d 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -58,6 +58,9 @@ properties:
       Identifies that the hart uses the RISC-V instruction set
       and identifies the type of the hart.
 
+  clocks:
+    maxItems: 1
+
   mmu-type:
     description:
       Identifies the MMU address translation mode used on this
-- 
2.39.2


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[PATCH v1 3/6] dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

With "additionalProperties: true" removed from cpus.yaml,
dtbs_check complains that #cooling-cells is a disallowed property.
Add a ref to the binding in which it is defined to satisfy the checks.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 3808a6703b2d..9bf2b72a9460 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -25,6 +25,7 @@ description: |
 
 allOf:
   - $ref: /schemas/cpu.yaml#
+  - $ref: /schemas/thermal/thermal-cooling-devices.yaml#
 
 properties:
   compatible:
-- 
2.39.2


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[PATCH v1 4/6] dt-bindings: riscv: cpus: permit operating-points-v2

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

To allow setting "unevaluatedProperties: false" for cpus.yaml, permit
the operating points property for RISC-V cpu nodes.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9bf2b72a9460..00d1e273f1a9 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -108,6 +108,7 @@ properties:
   # RISC-V has multiple properties for cache op block sizes as the sizes
   # differ between individual CBO extensions
   cache-op-block-size: false
+  operating-points-v2: true
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.39.2


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[PATCH v1 5/6] dt-bindings: riscv: cpus: document cpu-supply

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

To facilitate switching to "unevaluatedProperties: false", document the
cpu-supply property that is already in use in several Allwinner
devicetrees.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 00d1e273f1a9..5e2db35411f1 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -62,6 +62,10 @@ properties:
   clocks:
     maxItems: 1
 
+  cpu-supply:
+    description:
+      Regulator supplying the CPU's power rail.
+
   mmu-type:
     description:
       Identifies the MMU address translation mode used on this
-- 
2.39.2


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[PATCH v1 6/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

To permit validation of cpu nodes, swap "additionalProperties: true"
out for "unevaluatedProperties: false".

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 5e2db35411f1..d82d5c872a0e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -152,7 +152,7 @@ required:
   - riscv,isa
   - interrupt-controller
 
-additionalProperties: true
+unevaluatedProperties: false
 
 examples:
   - |
-- 
2.39.2


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Re: [PATCH v1 0/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

[Rob Herring]

On Sat, Jun 10, 2023 at 06:24:47PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Do the various bits needed to drop the additionalProperties: true that
> we currently have in riscv/cpu.yaml, to permit actually enforcing what
> people put in cpus nodes.

Arm needs pretty much all the same properties. I started on adding them 
to cpu.yaml a while back. Let me finish that up.

> 
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> CC: Paul Walmsley <paul.walmsley@sifive.com>
> CC: Palmer Dabbelt <palmer@dabbelt.com>
> CC: linux-riscv@lists.infradead.org
> CC: devicetree@vger.kernel.org
> CC: linux-kernel@vger.kernel.org
> 
> Conor Dooley (6):
>   dt-bindings: riscv: cpus: add a ref the common cpu schema
>   dt-bindings: riscv: cpus: allow clocks property

I just have 'clocks: true', so if you want to keep this setting it to 1 
clock that's fine. But I imagine that it's just a matter of time until 
someone wants more clocks.

>   dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
>   dt-bindings: riscv: cpus: permit operating-points-v2
>   dt-bindings: riscv: cpus: document cpu-supply
>   dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
> 
>  .../devicetree/bindings/riscv/cpus.yaml         | 17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> -- 
> 2.39.2
> 

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Re: [PATCH v1 0/6] dt-bindings: riscv: cpus: switch to unevaluatedProperties: false

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1919 bytes --]

On Thu, Jun 15, 2023 at 11:47:34AM -0600, Rob Herring wrote:
> On Sat, Jun 10, 2023 at 06:24:47PM +0100, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > Do the various bits needed to drop the additionalProperties: true that
> > we currently have in riscv/cpu.yaml, to permit actually enforcing what
> > people put in cpus nodes.
> 
> Arm needs pretty much all the same properties. I started on adding them 
> to cpu.yaml a while back. Let me finish that up.

Cool, I see you've already updated dt-schema. I'll go update mine & cull
whatever is no longer needed here.

> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > CC: Paul Walmsley <paul.walmsley@sifive.com>
> > CC: Palmer Dabbelt <palmer@dabbelt.com>
> > CC: linux-riscv@lists.infradead.org
> > CC: devicetree@vger.kernel.org
> > CC: linux-kernel@vger.kernel.org
> > 
> > Conor Dooley (6):
> >   dt-bindings: riscv: cpus: add a ref the common cpu schema
> >   dt-bindings: riscv: cpus: allow clocks property
> 
> I just have 'clocks: true', so if you want to keep this setting it to 1 
> clock that's fine. But I imagine that it's just a matter of time until 
> someone wants more clocks.

Yeah, I said something to that affect in the commit message. I don't
doubt that it'll show up at some point, was just enabling the minimum
that I know of SoCs requiring at the moment. "clocks: true" WFM.

Cheers,
Conor.

> >   dt-bindings: riscv: cpus: add a ref to thermal-cooling-cells
> >   dt-bindings: riscv: cpus: permit operating-points-v2
> >   dt-bindings: riscv: cpus: document cpu-supply
> >   dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
> > 
> >  .../devicetree/bindings/riscv/cpus.yaml         | 17 ++++++++++++++++-
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> > 
> > -- 
> > 2.39.2
> > 

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