From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org
Subject: [PATCH v5 0/1] Risc-V Svinval support
Date: Fri, 23 Jun 2023 18:08:48 +0530 [thread overview]
Message-ID: <20230623123849.1425805-1-mchitale@ventanamicro.com> (raw)
This patch adds support for the Svinval extension as defined in the
Risc V Privileged specification.
Changes in v5:
- Reduce tlb flush threshold to 64
- Improve implementation of local_flush_tlb* functions
Changes in v4:
- Rebase and refactor as per latest changes on torvalds/master
- Drop patch 1 in the series
Changes in v3:
- Fix incorrect vma used for sinval instructions
- Use unified static key mechanism for svinval
- Rebased on torvalds/master
Changes in v2:
- Rebased on 5.18-rc3
- update riscv_fill_hwcap to probe Svinval extension
Mayuresh Chitale (1):
riscv: mm: use svinval instructions instead of sfence.vma
arch/riscv/include/asm/tlbflush.h | 1 +
arch/riscv/mm/tlbflush.c | 66 +++++++++++++++++++++++++++----
2 files changed, 59 insertions(+), 8 deletions(-)
--
2.34.1
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next reply other threads:[~2023-06-23 12:39 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-23 12:38 Mayuresh Chitale [this message]
2023-06-23 12:38 ` [PATCH v5 1/1] riscv: mm: use svinval instructions instead of sfence.vma Mayuresh Chitale
2023-06-24 11:04 ` Andrew Jones
2023-09-25 15:12 ` [PATCH v5 0/1] Risc-V Svinval support Palmer Dabbelt
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