From: Palmer Dabbelt <palmer@dabbelt.com>
To: mchitale@ventanamicro.com
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
aou@eecs.berkeley.edu, mchitale@ventanamicro.com,
atishp@atishpatra.org, anup@brainfault.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v5 0/1] Risc-V Svinval support
Date: Mon, 25 Sep 2023 08:12:25 -0700 (PDT) [thread overview]
Message-ID: <mhng-f799bd2b-7f22-4c03-bdb2-903fa3b5d508@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230623123849.1425805-1-mchitale@ventanamicro.com>
On Fri, 23 Jun 2023 05:38:48 PDT (-0700), mchitale@ventanamicro.com wrote:
> This patch adds support for the Svinval extension as defined in the
> Risc V Privileged specification.
Do you have benchmarks (like we asked for here
<https://lore.kernel.org/all/CAN37VV40msnohyJqkwW_YkUmXmEL1yztk+ZQhTeA6feS-W0S2g@mail.gmail.com/>)?
>
> Changes in v5:
> - Reduce tlb flush threshold to 64
> - Improve implementation of local_flush_tlb* functions
>
> Changes in v4:
> - Rebase and refactor as per latest changes on torvalds/master
> - Drop patch 1 in the series
>
> Changes in v3:
> - Fix incorrect vma used for sinval instructions
> - Use unified static key mechanism for svinval
> - Rebased on torvalds/master
>
> Changes in v2:
> - Rebased on 5.18-rc3
> - update riscv_fill_hwcap to probe Svinval extension
>
>
> Mayuresh Chitale (1):
> riscv: mm: use svinval instructions instead of sfence.vma
>
> arch/riscv/include/asm/tlbflush.h | 1 +
> arch/riscv/mm/tlbflush.c | 66 +++++++++++++++++++++++++++----
> 2 files changed, 59 insertions(+), 8 deletions(-)
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prev parent reply other threads:[~2023-09-25 15:12 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-23 12:38 [PATCH v5 0/1] Risc-V Svinval support Mayuresh Chitale
2023-06-23 12:38 ` [PATCH v5 1/1] riscv: mm: use svinval instructions instead of sfence.vma Mayuresh Chitale
2023-06-24 11:04 ` Andrew Jones
2023-09-25 15:12 ` Palmer Dabbelt [this message]
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