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From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Conor Dooley <conor@kernel.org>,
	Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Hal Feng <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>,
	"William Qiu" <william.qiu@starfivetech.com>,
	<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
Date: Tue, 4 Jul 2023 14:46:06 +0800	[thread overview]
Message-ID: <20230704064610.292603-4-xingyu.wu@starfivetech.com> (raw)
In-Reply-To: <20230704064610.292603-1-xingyu.wu@starfivetech.com>

Add PLL clock inputs from PLL clock generator.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../bindings/clock/starfive,jh7110-syscrg.yaml | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
index 84373ae31644..5ba0a885aa80 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
@@ -27,6 +27,9 @@ properties:
           - description: External I2S RX left/right channel clock
           - description: External TDM clock
           - description: External audio master clock
+          - description: PLL0
+          - description: PLL1
+          - description: PLL2
 
       - items:
           - description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties:
           - description: External I2S RX left/right channel clock
           - description: External TDM clock
           - description: External audio master clock
+          - description: PLL0
+          - description: PLL1
+          - description: PLL2
 
   clock-names:
     oneOf:
@@ -52,6 +58,9 @@ properties:
           - const: i2srx_lrck_ext
           - const: tdm_ext
           - const: mclk_ext
+          - const: pll0_out
+          - const: pll1_out
+          - const: pll2_out
 
       - items:
           - const: osc
@@ -63,6 +72,9 @@ properties:
           - const: i2srx_lrck_ext
           - const: tdm_ext
           - const: mclk_ext
+          - const: pll0_out
+          - const: pll1_out
+          - const: pll2_out
 
   '#clock-cells':
     const: 1
@@ -93,12 +105,14 @@ examples:
                  <&gmac1_rgmii_rxin>,
                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                 <&tdm_ext>, <&mclk_ext>;
+                 <&tdm_ext>, <&mclk_ext>,
+                 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
         clock-names = "osc", "gmac1_rmii_refin",
                       "gmac1_rgmii_rxin",
                       "i2stx_bclk_ext", "i2stx_lrck_ext",
                       "i2srx_bclk_ext", "i2srx_lrck_ext",
-                      "tdm_ext", "mclk_ext";
+                      "tdm_ext", "mclk_ext",
+                      "pll0_out", "pll1_out", "pll2_out";
         #clock-cells = <1>;
         #reset-cells = <1>;
     };
-- 
2.25.1


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  parent reply	other threads:[~2023-07-04  6:49 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-04  6:46 [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-04  6:46 ` [RESEND PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-13 12:26   ` Emil Renner Berthing
2023-07-14  6:24     ` Xingyu Wu
2023-07-04  6:46 ` [RESEND PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-04 22:21   ` Conor Dooley
2023-07-05  6:29   ` Krzysztof Kozlowski
2023-07-13 12:31   ` Emil Renner Berthing
2023-07-04  6:46 ` Xingyu Wu [this message]
2023-07-04 22:23   ` [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Conor Dooley
2023-07-07  7:45     ` Xingyu Wu
2023-07-13 12:34   ` Emil Renner Berthing
2023-07-04  6:46 ` [RESEND PATCH v6 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-13 12:37   ` Emil Renner Berthing
2023-07-04  6:46 ` [RESEND PATCH v6 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-04 22:25   ` Conor Dooley
2023-07-12  3:24   ` Hal Feng
2023-07-13 13:15   ` Emil Renner Berthing
2023-07-14  8:01     ` Xingyu Wu
2023-07-14  9:36       ` Emil Renner Berthing
2023-07-04  6:46 ` [RESEND PATCH v6 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-13 13:21   ` Emil Renner Berthing
2023-07-04  6:46 ` [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-13 13:24   ` Emil Renner Berthing
2023-07-04 22:29 ` [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Conor Dooley
2023-07-12 16:09   ` Conor Dooley
2023-07-05  6:27 ` Krzysztof Kozlowski
2023-07-07  7:41   ` Xingyu Wu

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